International Business Machines Corporation

Mark S Fredrickson

Scott Douglas Frei

Chad Balling McBride

Chad M Albertson

David Grant Wheeler

Steven Paul Jones

Glen Howard Handlogten

John Michael Borkenhagen

David John Krolak

Mark David Bellows

Charles Ray Johns

Jeb R Linton

John David Irish

Jeffrey Douglas Brown

Scott Douglas Clark

Scott Michael Willenborg

Anthony DeGroff Drumm

Brian C Wilson

Spencer K Millican

Michael A Muston

Marcus Matthew Poplawski

Described are techniques for presentation attack detection including a computer-implemented method of emitting a predetermined frequency pattern using at least one speaker communicatively coupled to a computer implementing a video-conference. The computer-implemented method further comprises collecting, by a camera communicatively coupled to the computer and overlapping with the emitting the predetermined frequency pattern, video data of a user engaged in the video-conference. The computer-implemented method further comprises determining that the video data is inconsistent with an expected response to the predetermined frequency pattern. The computer-implemented method further comprises generating an indication that the user engaged in the video-conference is performing a presentation attack.

Sound-based presentation attack detection

Techniques for authentication of digital recordings are provided. An element of encrypted data is output in a recording environment. The element of encrypted data, embedded in a digital recording comprising at least one of audio data and image data captured in the recording environment, is extracted. A decrypted value is generated based on a private key and the first element of encrypted data, and the first decrypted value and a stored value associated with a first element of the digital recording are compared. The digital recording is authenticated based on the first decrypted value substantially matching the stored value.

Authenticating digital recordings

Aspects described herein include a computer-implemented method (and related system and computer program product) comprising receiving, from a bonding service, an authorization request for a predefined authorized use of a good or service by a user. The authorization request indicates that the user meets one or more predefined criteria for the predefined authorized use. The method further comprises determining one or more penalty conditions of a bonding agreement for the predefined authorized use by the user, and receiving, from the bonding service, a confirmation that the user agrees to meet the one or more penalty conditions of the bonding agreement. The method further comprises receiving, from an owner of the good or service, an authorization of the authorization request, and transmitting, responsive to authorization of the authorization request, a token to the bonding service that enables the user to access the predefined authorized use of the good or service.

Authorizing uses of goods or services using bonding agreement

Techniques for analysis of verification parameters and reduction of training data are provided. A plurality of test results is received, where each of the plurality of test results specifies a respective one or more parameters and a respective one or more events. A list of parameters used to stimulate computing logic is determined. Additionally, a plurality of relevant parameters is generated, corresponding to parameters in the list of parameters that have at least two distinct values specified in the plurality of test results. A plurality of training cases is generated based on the plurality of test results and the plurality of relevant parameters. Further, a neural network is generated for design verification of the computing logic based on the plurality of relevant parameters. The neural network is trained based on the plurality of training cases.

Analysis of verification parameters for training reduction

A computer system, processor, and method for processing information is disclosed that includes watching logical operations to detect unauthorized attempts to access a register, and taking evasive action in response to detecting unauthorized attempts to access the register. In an embodiment, the register is a hidden, secret, restricted, or undocumented register, and the method further includes, in response to unauthorized attempts to access the secret register, locking the contents of the secret register. The evasive action may include one or more of interrupting the operations of the processor; causing the processor to shut-down, malfunction, lock, self-destruct; no longer providing read or write permission or access to the register; releasing data disguised to look like the real register data while not releasing the real data; and combinations thereof.

Methods to discourage unauthorized register access

Techniques for enhanced security for disconnected devices are provided. A request for one or more attributes of a security component is received by the security component, from a requesting device. The one or more attributes are provided to the requesting device, where the requesting device transmits the one or more attributes to a network service, where the security component is not able to communicate with the network service. A token is received from the requesting device, where the requesting device received the token in response to transmitting the one or more attributes to the network service. A level of access is determined for the requesting device, based on validating the token using a predefined configuration of the security component. Finally, the determined level of access is provided to the requesting device.

Network-based authorization for disconnected devices

Performing an operation comprising extracting a first element of encrypted data embedded in a digital recording comprising at least one of audio data and image data captured in a recording environment, generating a first decrypted value, the generating performed by execution of a cryptography algorithm based on a private key and the first element of encrypted data, comparing the first decrypted value and a stored value associated with a first element of the digital recording, and authenticating the digital recording based on the first decrypted value substantially matching the stored value.

Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a 'claimed' state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.

Techniques for faster loading of data for accelerators

Embodiments herein describe a switchboard coupled to a system bus in an integrated circuit for managing the flow of data between different entities coupled to the bus (e.g., processing cores, accelerators, memory controllers, input/output (I/O) interfaces, and the like). The switchboard is a hardware module that may be tasked with assigning different system bus addresses (or range of addresses) to each of the entities coupled to the bus. These addresses may be unique such that each entity can be uniquely identified by its assigned address. The address space of the system bus also includes managed address that are reserved&#x2014;i.e., are not assigned to any particular entity. The switchboard is tasked with assigning the managed addresses (also referred to as virtual channels) to an entity which can be used to enable direct communication between hardware entities using the system bus.

Communicating in an integrated circuit using hardware-managed virtual channels

A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.

Delayed execution of program code on multiple processors

Methods and systems with delayed execution of multiple processors

An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.

Heuristic clustering of circuit elements in a circuit design

In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.

Methods and apparatus for reducing command processing latency while maintaining coherence

Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.

Growing community of inventors

Rochester, MN, United States of America

Mark S Fredrickson