International Business Machines Corporation

Mark S Farrell

Charles W Gainey, Jr

Timothy John Slegel

Donald W Schmidt

Jeffrey Paul Kubala

Damian Leo Osisek

Lisa Cranton Heller

Charles Franklin Webb

Dan F Greiner

Fadi Y Busaba

Jonathan D Bradbury

Christian Jacobi

Bruce C Giamei

David F Craddock

Thomas Anthony Gregg

Peter Kenneth Szwed

Chung-Lung K Shum

Gustav E Sittmann, Iii

Mark Anthony Check

James H Mulder

Robert R Rogers

Matthias Klein

John Stephen Liptay

Barry Watson Krumm

Janet R Easton

Bernard R Pierce

Brian L Smith

Martin Recktenwald

Beth A Glendening

Aditya Nitin Puranik

Timothy J Siegel

Marcel Mitran

Khary J Alexander

Christian Zoellin

Simon Weishaupt

Richard K Errickson

Frank William Brice

Anthony Thomas Sofia

Ronald Morton Smith, Sr

Pak-kin Mak

Scott Barnett Swaney

Klaus Meissner

Eberhard Engler

Ashutosh Misra

Girish Gopala Kurup

Ugochukwu Charles Njoku

Jennifer A Navarro

Wen H Li

Brenton F Belmar

Carol B Hernandez

Donald W McCauley

Eric M Schwarz

Harry M Yudenfriend

Patrick James Meaney

Dale Francis Riedy, Jr

Peter Grimm Sutton

Giora Biran

William J Rooney

Elpida Tzortzatos

Eric N Lais

Louis P Gomes

Kevin Alexander Stoodley

Bernd Nerz

Jonathan T Hsieh

John G Rell, Jr

Peter Jeremy Relson

David Andrew Schroter

Michael Billeci

Greg A Dyck

Dean G Bair

Karl J Duvalsaint

Rebecca S Wisniewski

Ashutosh Mishra

Steven R Carlough

Michael F Fee

Yuen H Chan

Christopher A Krygowski

Michael Andrew Blake

Leslie W Wyman

Craig Raymond Walters

Timothy Carl Bronson

Frank Siegfried Lehnert

Garrett M Drapala

Richard P Tarcza

John Robert Ehrman

Casper A Scalzi

Kulwant M Pandey

Gary E Strait

Roger E Hough

William J Lewis

Hieu Trong Huynh

Robert M Abrams

Mike Stephen Fulton

Anthony F Coneski

Peter H Gum

Michael P Mullen

Mahmoud Amin

Douglas G Balazich

Liyong Wang

Christopher Raymond Conklin

Storage accesses for merge operations are minimized. A plurality of records of a plurality of input lists are merged. The merging includes determining that an input list of the plurality of input lists has become empty, and checking, based on determining that the input list has become empty, a control specific for the input list. The control is used to determine how to proceed, such as whether to end merging or continue merging.

Controlling storage accesses for merge operations

A method is provided that is executable by a processor of a computer. Note that the processor is communicatively coupled to a memory of the computer, and the memory stores a response block of a call command. In implementing the method, the processor defines a sub-functions field in the response block of the call command. Further the processor indicates that a set of functions of a set of instructions are installed and available at an interface based on a corresponding sub-functions flag within the sub-functions field being set. Note that the interface is also being executed on the computer and that the set of functions being represented by the corresponding sub-functions flag. The processor further indicates that the set of functions of the set of instructions are not installed based on the corresponding sub-functions flag not being set.

Extended asynchronous data mover functions compatibility indication

A method is provided that includes receiving, by a firmware from an originating software, an asynchronous request for an instruction of an algorithm for compression of data. The firmware operates on a first processor and the originating software operates on a second processor. The firmware issues a synchronous request to the first processor to cause the processor to execute the instruction synchronously. It is determined, by the firmware, whether an interrupt is received from the first processor with respect to the first processor executing the instruction. The firmware retries the issuance of the synchronous request each time the interrupt is received until a retry threshold is reached.

Functional completion when retrying a non-interruptible instruction in a bi-modal execution environment

Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Saving and restoring machine state between multiple executions of an instruction

A system is provided and includes a plurality of machines. The plurality of machines includes a first generation machine and a second generation machine. Each of the plurality of machines includes a machine version. The first generation machine executes a first virtual machine and a virtual architecture level. The second generation machine executes a second virtual machine and the virtual architecture level. The virtual architecture level provides a compatibility level for a complex interruptible instruction to the first and second virtual machines. The compatibility level is architected for a lowest common denominator machine version across the plurality of machines. The compatibility level includes a lowest common denominator indicator identifying the lowest common denominator machine version.

Maintaining compatibility for complex functions over multiple machine generations

A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

Sort and merge instruction for a general-purpose processor

A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

Efficiency for coordinated start interpretive execution exit for a multithreaded processor

Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

Instructions controlling access to shared registers of a multi-threaded processor

Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.

Verifying the correctness of a deflate compression accelerator

A system and method of implementing a wait state for a plurality of threads executing on a computer processor core of the processor. The processor is configured to execute instruction streams by the plurality of threads, wherein the plurality of threads includes a first thread and a set of remaining threads and determine that the first thread has entered a first wait state loop. The processor is also configured to determine that any of the set of remaining threads has not entered a corresponding wait state loop and remain by the first thread in the first wait state loop until each of the set of remaining threads has entered the corresponding wait state loop.

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Pleasant Valley, NY, United States of America

Mark S Farrell