Raytheon Company

Mark S Durschlag

Thomas E Kazior

James L Vorhaus

Barry J Liles

Kyu-Woong Lee

James G Oakes

John Day

A semiconductor structure is described having a first electrode and a second electrode disposed on a surface of the structure and a bridging conductor connected between the first electrode and the second electrode. The bridging conductor includes a plurality of layers of different metals wherein the plurality of layers of different metals includes a layer of refractory metal adjacent a layer of electrically conductive metal. In a preferred embodiment, the refractory metal is titanium and the electrically conductive metal is gold. With such an arrangement, a semiconductor structure is provided which is effective in preventing restructuring due to mechanical stresses induced in the metal by dissimilar thermal expansion coefficients when electrical pulsing cycles the temperature of the semiconductor structure.

Semiconductor structures and method of manufacturing

A method of simultaneously forming recesses for via holes and tube structures in a substrate is provided in a common etching step by defining a mask pattern for the via hole as a single aperture and by defining a mask pattern for the tub structure as a plurality of thin slots. The slots are chosen to have a smaller cross-sectional dimension than the corresponding dimension for the single aperture. Etchant brought into contact with the substrate will etch the substrate at a slower rate in the slots than in the single aperture such that the via hole will etch completely through the substrate whereas, the tub structure will be etched only partially through the substrate. Conductive material is provided in the tub structure and via hole, and a layer of conductive material is disposed thereover, to provide a heat sink/ground plane conductor. Electrical contact is provided between the frontside of the substrate and the heat sink/ground plane conductor through the via hole, whereas a low thermal impedance path is provided through the tub structure between a heat dissipating element supported on the frontside of the substrate and the heat sink/ground plane conductor.

Simultaneous formation of via hole and tube structures for GaAs

A method of simultaneously forming recesses for via holes and tub structures in a substrate is provided in a common etching step by defining a mask pattern for the via hole as a single aperture and by defining a mask pattern for the tub structure as a plurality of thin slots. The slots are chosen to have a smaller cross-sectional dimension than the corresponding dimension for the single aperture. Etchant brought into contact with the substrate will etch the substrate at a slower rate in the slots than in the single apertur such that the via hole will etch completely through the substrate whereas, the tub structure will be etched only partially through the substrate. Conductive material is provided in the tub structure and via hole, and a layer of conductive material is disposed thereover, to provide a heat sink/ ground plane conductor. Electrical contact is provided between the frontside of the substrate and the heat sink/ground plane conductor through the via hole, whereas a low thermal impedance path is provided through the tube structure between a heat dissipating element supported on the frontside of the substrate and the heat sink/ground plane conductor.

Simultaneous formation of via hole and tub structures for GaAs

A first masking layer of a first resist is provided over a semiconductor substrate and is patterned in a selected region to provide a masked region over which an airbridge interconnect will be provided. A second relatively thick layer of a second, different type of resist and a third relatively thin layer of resist are provided, respectively, over the substrate. The second and third layers of resist are patterned to provide an aperture having overhanging portions exposing the previously applied patterned regions of the first layer, and selected adjacent portions of the substrate. The second and third layers may also be patterned to provide a region for a patterned strip conductor. A stream of evaporated metal is directed towards the substrate and deposited within the apertures to provide an airbridge interconnect conductor and patterned strip conductor. The overhanging portions of the apertures provide separation between the metal layer deposited within the aperture and the metal layer deposited over the third masking layer, allowing the second and third masking layers to be lifted-off without disturbing the conductors. The masked regions underlying the bridges are also removed leaving the airbridge interconnect and patterned strip conductor.

Evaporated thick metal and airbridge interconnects and method of

Lumped passive components including a capacitor having a silicon nitride dielectric, a tantalum film resistor, and a capacitor having a tantalum oxide dielectric are formed on a semi-insulating substrate by first providing an insulating layer, here of silicon nitride, over the substrate and metal contacts having previously been formed on such substrate. The metal contacts provide a first plate for each one of such capacitors. A tantalum layer is reactively sputtered on the insulating layer, and a protective masking layer is next provided on such tantalum layer. An area where the anodized tantalum capacitor is to be formed is then opened in the protective masking layer over a selected one of the metal contacts. A portion of the tantalum is anodized in such area to form an area of a tantalum oxide (Ta.sub.2 O.sub.5). The area where the tantalum oxide is formed is confined generally to the area in the tantalum layer over the contact. The masking layer is removed and a second masking layer is patterned to provide an etching mask used to etch the tantalum layer to define each one of such capacitors, and to provide a strip of tantalum, defining a region for said tantalum resistor. Top metal contacts are then provided aligned with the first set of such contacts, and thus providing a second metal plate of the anodized tantalum capacitor and a second metal plate of the silicon nitride capacitor. Further, a set of metal contacts is provided to each end of the tantalum strip to provide the tantalum resistor.

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Natick, MA, United States of America

Mark S Durschlag