Advanced Micro Devices Corporation

Spansion LLC.

Other

Fujitsu Corporation

Fujitsu Amd Semiconductor Limited

Globalfoundries Inc.

Mark S Chang

Angela Tai Hui

Fei Wang

Hao Fang

Robin W Cheung

Minh Van Ngo

Ramkumar Subramanian

Mark T Ramsbey

Christopher F Lyons

Yu Nan Sun

Scott Allan Bell

Chi K Chang

Sergey D Lopatin

Lu You

Tatsuya Kajita

King Wai Kelwin Ko

Unsoon Kim

Chih Yuh Yang

Hung-Sheng Chen

Kuo-Tung Chang

Hiroyuki Kinoshita

Richard J Huang

Dawn M Hopper

Douglas J Bonser

Patrick K Cheung

Jane V Oglesby

Bharath Rangarajan

Michael K Templeton

Srikanteswara Dakshina-Murthy

Marina V Plat

Yue-Song He

Ning Cheng

David Keating Foote

Darin A Chan

Lewis N Shen

Maria Chow Chan

Jack F Thomas

Phillip Lawrence Jones

Kyunghoon Min

Matthew S Buynoski

Calvin T Gabriel

Shenqing Fang

Yowjuang William Liu

Mark W Randolph

Suzette Keefe Pangrle

Nicholas H Tripsas

Uzodinma Okoroanyanwu

Alexander H Nickel

Marilyn I Wright

Stephen Keetai Park

Harpreet Kaur Sachar

Minh-Van Ngo

Jihwan Choi

Ashok M Khathuria

Zubin Patel

Sheshadri Ramaswami

Ming-Ren Lin

Eric N Paton

John JianShi Wang

Chih-Yuh Yang

Yider Wu

Kent Kuohua Chang

Wenge Yang

Kouros Ghandehari

Philip A Fisher

Jayendra D Bhakta

Emmanuil Lingunis

Pei-Yuan Gao

Weidong Qian

Jusuke Ogura

James J Xie

Kevin Song

Mohammad R Rakhshandehroo

Stephan Keetai Park

Mike Templeton

Brian Osborn

Yu Sun

A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

Integrated circuit with metal and semi-conducting gate

A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

Method and system for providing contact to a first polysilicon layer in a flash memory device

Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

Selective silicide formation using resist etch back

Integrated circuit system with metal and semi-conducting gate

A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications

Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications

Selective silicide formation using resist etchback

A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.

Selective contact formation using masking and resist patterning techniques

A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

Shallow trench isolation approach for improved STI corner rounding

A method of making an organic memory cell which comprises two electrodes with a controllably conductive media between the two electrodes is disclosed. The present invention involves providing a dielectric layer having formed therein one or more first electrode pads; removing a portion of the first electrode pad to form a recessed area on top of the pads and in the dielectric layer using reverse electroplating; forming a controllably conductive media over the first electrode pad in the recessed area; and forming a second electrode over the conductive media. The controllably conductive media contains an organic semiconductor layer and a passive layer.

Method of making an organic memory cell

A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.

Etch process for CD reduction of arc material

A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer of polycrystalline silicon formed on a surface of the interface layer.

Interface layer between dual polycrystalline silicon layers

Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.

Sidewall formation for high density polymer memory element array

Growing community of inventors

Los Altos, CA, United States of America

Mark S Chang