Motorola Corporation

Freescale Semiconductor,inc.

Mark S Aurora

Patrice M Parris

Bruce L Morton

Walter J Ciosek

Robert T Smith

Robert Arthur Jensen

Robert Eugene Smith

Brian E Cook

Alex S Yap

James S Ledford

An integrated circuit has a Built-In Self-Test (BIST) controller ( ) that has a sequencer ( ) that provides test algorithm information for multiple memories ( ). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces ( ) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. This timing information is read prior to performing the test algorithm and is used in performing the test algorithm.

Multiple level built-in self-test controller and method therefor

A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide &ldquo;1&rdquo; outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide &ldquo;0&rdquo; outputs from selected cells.

Ultra-late programming ROM and method of manufacture

A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide &ldquo;1&rdquo; outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide &ldquo;0&rdquo; outputs from selected cells.

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Austin, TX, United States of America

Mark S Aurora