Delphi Technologies, Inc.

Delco Electronics Corporation

Borgwarner US Technologies LLC

Delphi Technologies IP Limited

Mark Russell Keyse

Seyed R Zarabadi

Gregory J Manlove

Brian K Good

Jack Lavern Glenn

Mark Wendell Gose

Marc R Engelhardt

Pedro E Castillo-Borelly

Mark Billings Kearney

Kevin M Gertiser

Walter Kirk Kosiak

Peter Allan Laubenstein

Richard Joseph Ravas

Srikanth Vijaykumar

Jingyi Hou

Thomas Gerard Block

Ihab Nahlus

William Joseph Hulka

Subhashrahul Shekhar

A system comprises an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic isolator separating a high voltage area from a low voltage area; a low voltage phase controller in the low voltage area, the low voltage phase controller configured to receive a clock reference signal; and a high voltage phase controller in the high voltage area, the high voltage phase controller configured to align a clock reference signal of the high voltage phase controller with the clock reference signal of the low voltage phase controller.

Systems and methods for oscillator calibrator for inverter for electric vehicle

An apparatus includes a first analog-to-digital converter configured to measure a first reference voltage and a third reference voltage. The apparatus also includes a second analog-to-digital converter configured to measure a second reference voltage and a fourth reference voltage. The apparatus also includes a controller configured to calculate a first resistance ratio, and determine a positive high voltage associated with the positive high voltage direct current input signal based, at least in part, on the first resistance ratio. The controller is further configured to calculate a second resistance ratio, and determine a negative high voltage associated with the negative high voltage direct current input signal based, at least in part, on the second resistance ratio.

System and method for high voltage battery pack measurement

A system comprises an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic isolator separating a high voltage area from a low voltage area; a low voltage phase controller in the low voltage area, the low voltage phase controller configured to receive a pulse width modulation (PWM) signal from an inverter controller and adjust the received PWM signal based on a feedback signal; and a high voltage phase controller in the high voltage area, the high voltage phase controller configured to receive the adjusted PWM signal from the low voltage phase controller, provide the adjusted PWM signal to a phase switch, and provide the feedback signal based on an on-time measurement of the phase switch.

Systems and methods for phase switch timing controller for inverter for electric vehicle

A system includes an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic interface configured to separate a high voltage area from a low voltage area; a low voltage message manager in the low voltage area; a high voltage message manager in the high voltage area, and configured to communicate with the low voltage message manager; and a point-of-use message manager in the high voltage area, and configured to communicate with the high voltage message manager.

Systems and methods for bidirectional message architecture for inverter for electric vehicle

A method for fail-safe resolver excitation includes generating a resolver excitation signal and providing the resolver excitation signal to an input of a first resolver control circuit and to an input of a second resolver control circuit. The method also includes, in response to the first resolver control circuit detecting a fault in the resolver excitation signal provided to the first resolver control circuit: biasing, using the first resolver control circuit, a first resolver amplifier; and communicating, via a communication bus between the first resolver control circuit and the second resolver control circuit, an indication to the second resolver control circuit that the first resolver control circuit detected the fault in the resolver excitation signal provided to the first resolver control circuit.

Systems and methods for fail-safe resolver excitation

A method for regulating a power conditioner output voltage level includes monitoring a first voltage level of a first supply source and a second voltage level of a second supply source and, while the power conditioner is being supplied by the first supply source, controlling a duty-cycle of an output switch of the power conditioner with feedback-based control signals generated based on errors between a target voltage level and samples of the output voltage level obtained at an output voltage sampling frequency. The method also includes, controlling, for a period corresponding to the output voltage sampling frequency, the duty-cycle of the output switch with an estimated control signal. The method also includes, while the power conditioner is being supplied by the second supply source, controlling the duty-cycle of the output switch using the feedback-based control signals.

System and method for regulating output voltage level of a power conditioner

A battery monitor system for determining a cell voltage between a low side contact and a high side contact of a cell in situ as one of a plurality of cells connected in series to form a battery. The system uses an arrangement of switches and capacitors to shift relatively high absolute voltages of a battery stack to a relative low voltage level so lower voltage electronics can be used to monitor cell voltages. The system may be configured to provide a single ended measurement or a differential measurement indicative of a cell voltage. The differential measurement may be advantageous to correct or offset signal noise caused by electromagnetic interference (EMI).

Battery stack cell monitor

Analog signal conditioning circuitry is provided for processing an analog signal generated by a sensor to remove DC offset. The signal conditioning circuitry includes an amplifier having the first input receiving an analog input signal and a second input receiving a reference signal. The amplifier includes an output providing an analog output signal defined by an amplified representation of the analog input signal and the reference signal. The circuitry includes a feedback circuit having an input coupled to the amplifier output and an output coupled to the first input of the amplifier for providing an analog feedback signal. The feedback circuit includes an analog-to-digital converter for converting the analog amplifier output to a digital signal, a digital controller for processing the digital signal, and a digital to analog converter for converting the processed digital signal to an analog feedback signal.

Analog signal conditioning circuit having feedback offset cancellation

An analog signal gain circuit includes an input receiving an analog input signal defined by an ac signal component due to a driving force and a dc offset component independent of the driving force and an output providing an analog output signal defined by an amplified representation of the analog input signal and a dc offset component corresponding to a reference signal. A digital/analog feedback circuit includes a comparator having the reference signal as a switching threshold connected to an up/down counter having a number of digital outputs. The outputs of the up/down counter are connected to a D/A converter which converts the digital count to an analog feedback signal. The feedback signal is provided to the input of the analog signal gain circuit to minimize variations in the dc offset signal component of the analog output signal by compensating for the dc offset signal component of the analog input signal. The up/down counter is clocked at a slow rate to thereby provide a long time constant for minimizing the dc offset signal component.

Analog/digital feedback circuitry for minimizing DC offset variations in an analog signal

A DC offset compensation circuit (,) for compensating for a DC offset voltage of a signal amplifier (,) includes a first sample and hold circuit (,) having an input receiving an amplifier output signal (VOUT,) and an output supplying the sampled and held output signal (VOUT,) to a non-inverting input of a comparator,A first digital-to-analog (D/A) circuit (,) is responsive to a number of digital input signals to produce an analog DC target signal at an output (V,) thereof. The analog DC target signal is provided to an input of a second sample and hold circuit (,) having an output supplying the sampled and held analog DC target signal to an inverting input of the comparator,The output of the comparator,is provided to an offset cancellation control circuit (,) including a state machine (,) and a counter circuit (,) operable to modify a count value (OFFDAC) thereof depending upon statuses of a number of input control signals (CLK,CLK,STRT, STP) and the comparator output signal (CO). A second D/A circuit has a number of digital inputs receiving the count value (OFFDAC) and producing at an output (VDCO) thereof an analog DC compensation signal corresponding thereto. The analog DC compensation signal is provided to a input (VDCO) of the signal amplifier (,) to thereby force the DC component of the amplifier output signal (VOUT,) near the analog DC target signal, thereby minimizing an aggregate DC offset voltage attributable to the signal amplifier (,).

DC offset compensation circuit for a signal amplifier

A time-dependent piecewise linear signal generating circuit includes a first circuit responsive to a trigger signal to provide a number of time region signals each corresponding to a separate predefined time window of the piecewise linear signal, and a second circuit responsive to some of the time region signals to produce slope signals corresponding thereto, wherein each of the slope signals define a slope of the piecewise linear signal during a respective one of the time windows. A third circuit is responsive to the slope signals and the time region signals to produce the piecewise linear signal.

Piecewise linear signal generating circuit

A cross-coupled latch circuit that is a one-time programmable latch that allows volatile temporary writes to the latch prior to permanent programming of the latch. The latch circuit includes first and second programmable FET devices that include poly-poly capacitators in series with the gate terminal of each device. A pair of PMOS FET devices combine with the programmable devices to make up the latch. The latch circuit includes other FET devices that are switched on and off depending on whether the latch is being permanently programmed, temporarily written to, or reset. A NAND gate is provided such that a logical high output on the NAND gate allows the first programmable device to be temporarily programmed with a logical one and permanently programmed with a logical zero. A NOR gate is provided such that a logical high on the NOR gate allows the second programmable device to be temporarily programmed with a logical zero and permanently programmed with a logical one.

One-time programmable latch which allows volatile writes prior to

In accordance with the teachings of the present invention, a fault detection circuit is provided which detects short circuits on differential leads associated with a magnetic sensor and modifies said differential voltage to avoid possible errors associated with a short circuit. The circuit includes a first and second input coupled to first and second signal lines for receiving a differential voltage. A first voltage comparator compares voltage potentials at the first and second signal lines so as to detect equal voltage crossings and provide an output in response thereto. A rectifier is coupled to the first and second signal lines in the output of the first comparator and has first and second outputs for producing positive half-wave voltage cycles with a voltage potential at each of the first and second lead lines. A second comparator is provided for comparing the half-wave voltage cycles with a first threshold voltage that represents a short circuit power source. A third comparator is provided for comparing the half-wave voltage cycles with a second threshold voltage that represents a short circuit to ground. The voltage potentials at the first and second signal lines are converted to separate single-ended voltages when one of the second and third voltage comparators detects a short circuit so as to correct for possible errors caused by the short circuit.

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Sharpsville, IN, United States of America

Mark Russell Keyse