Intel Corporation

Mark Rowland

Ganapati Srinivasa

Krishnakanth Venkata Sistla

Vivek Garg

Avinash N Ananthakrishnan

Ankush Varma

Dean A Mulla

Ian M Steiner

Matthew M Bace

Jeffrey D Gilbert

Geeyarpuram N Santhanakrishnan

Daniel G Borkowski

Christopher J Shannon

Suresh Doraiswamy

Theodros Yigzaw

Michael F Cole

Chelsea Akturan

Cagdas Akturan

In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

Dynamically modifying a power/performance tradeoff based on a processor utilization

In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

Dynamically adjusting power of non-core processor circuitry including buffer circuitry

Dynamically modifying a power/performance tradeoff based on processor utilization

According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.

Performance prioritization in multi-threaded processors

A discussion of a dynamic configuration for a prefetcher is proposed. For example, a thread specific latency metric is calculated and provides dynamic feedback to the software on a per thread basis via the configuration and status registers. Likewise, the software can optionally use the information from the registers to dynamically configure the prefetching behavior and allows the software to be able to both query the performance and configure the prefetcher.

Method, apparatus, and a system for dynamically configuring a prefetcher based on a thread specific latency metric

A cache line replacement protocol for selecting a cache line for replacement based at least in part on the inter-cache traffic generated as a result of the cache line being replaced.

Method, system, and apparatus for an hierarchical cache line replacement

A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.

Cache eviction technique for reducing cache eviction traffic

Growing community of inventors

Beaverton, OR, United States of America

Mark Rowland