Silicon Graphics, Incorporated

Hewlett Packard Enterprise Development LP

Cray Research, Inc.

Silicon Graphics International Corporation

Mark Ronald Sikkink

Joseph Martin Placek

Randal Steven Passint

Russell Leonard Nicol

Nan Ma

Vernon W Swanson

John Francis De Ryckere

Frank R Dropps

William A Huffman

Stephen A Bowen

Richard B Salmonson

Stephen Cermak, Iii

David Paul Gruber

Kenneth A Van Goor

Thomas Alex Crapisi

Max C Logan

Jeffrey S Conger

Robert J Lutz

Richard G Finstad

Steven Shafer

Arthur H Orth

Gregory R Edlund

Terrance L Bowman

Mario J Rizzo

Robert J Greener

Karen Rae Beighley

Jonn Francis De Ryckere

Various embodiments improve the operation of computers by providing methods of transmitting data with low latency and high bandwidth. Data may be transmitted in a packet composed of data flits, the data flits having at least two different formats configured to implement different communication protocols. In some embodiments, a given flit may be transmitted using two different modulation methods, with a first part of the flit transmitted using a first modulation method, such as a binary method, and a second part of the flit using a higher-order modulation method.

Method and system for high speed data links

An apparatus and method detects trapped data at an intermediate node in a network path between a source node and a destination node, and re-routes that data to a downstream intermediate node in the network path via an alternate network path. An apparatus and method may include a virtualized physical interface, and may redirect the trapped data through a system's packet switched network, or through a system's flit switched network.

Adaptive routing for link-level retry protocol

A system, method, and storage medium provide dynamic, packet-based adaptive forward error correction over a lossy bidirectional data communication medium that couples a transmitting device to a receiving device. The transmitting device repeatedly transmits encoded data packets formed by applying, to unencoded data, a forward error correction (FEC) algorithm having a level N that indicates a number of correctable errors. The receiving device attempts to decode the encoded data packets using the FEC algorithm, requesting retransmission of a packet if there are too many errors to correct. The transmitting device decreases the level N when it does not receive such a request within a given duration. By contrast, the transmitting device increases the level N when it receives a sequence of such requests having a threshold length, each request being received less than the given duration after the previous request.

Packet-based adaptive forward error correction

A system and method provide a communications link having a plurality of lanes, and an in-band, real-time physical layer protocol that keeps all lanes on-line, while failing lanes are removed, for continuous service during fail over operations. Lane status is monitored real-time at the physical layer receiver, where link error rate, per lane error performance, and other channel metrics are known. If a lane failure is established, a single round trip request/acknowledge protocol exchange with the remote port completes the fail over. If a failing lane meets an acceptable performance level, it remains on-line during the round trip exchange, resulting in uninterrupted link service. Lanes may be brought in or out of service to meet reliability, availability, and power consumption goals.

High speed serial link in-band lane fail over for RAS and power management

A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.

Low latency serial data encoding scheme for enhanced burst error immunity and long term reliability

The present invention provides an interface and method for synchronous data transfer between domains clocked at different frequencies. The interface includes a first latch for receiving data from a first domain clocked at one frequency when the first latch is selected and a second latch for receiving data from the first domain when the second latch is selected. A third latch is provided for transferring data from either the first latch or the second latch to the second domain when the second domain is clocked.

Interface for synchronous data transfer between domains clocked at different frequencies

The present invention comprises a dual bank FIFO memory buffer operable to buffer read data from memory and thereby compensate for specific timing problems in certain computerized systems. One embodiment of the invention includes a dual bank FIFO that comprises a first bank of memory elements operable to buffer memory data and a second bank of memory elements operable to buffer memory data. Write control address logic is operable to store selected memory data in memory elements with selected addresses within a bank of memory elements, and write control timing logic is operable to selectively grant write access to the banks of memory elements at predetermined time. Also, read control logic operable to read data stored in the first and second banks.

Dual-bank FIFO for synchronization of read data in DDR SDRAM

New methods and configurations are provided that allow for a large memory capacity, as well as minimized interconnect distances between the memory chips and one or more processors, and the HUB chip-set. The apparatus, configurations and methods include providing a printed circuit board having one or more processor conductive portions and one or more z-axis connector conductive portions in close proximity with each other, and connecting the one or more processors on one side of a printed circuit board, and connecting the one or more z-axis connectors for the memory daughter cards on the opposite side of the processor board. Standoffs are used to support and secure the horizontally disposed z-axis memory daughter cards and to ensure proper spacing between the z-axis daughter cards and the processor board Standoffs include an alignment pin portion and a spacer portion. The alignment pin portion includes an alignment portion, foot, and urging portion. The spacer portion includes pin coupler, relief portion, and aperture. The standoff is inserted into an aperture of a first printed circuit board and turned 90 degrees to secure the spacer portion and the foot to the first printed circuit board. An aperture in a second printed circuit board is slid over the alignment pin portion, wherein the second printed circuit board rests on the spacer portion. The fastening means is used through an aperture in the second printed circuit board communicating with the spacer portion.

Memory daughter card apparatus, configurations, and methods

A composite delay line includes a first and a second delay line connected to a multiplexer. The multiplexer has a first and a second input. The first delay line includes an input, an output and first control means for controlling delay. The second delay line includes an input, an output and second control means for controlling delay. The output of each delay line is connected to the input of the multiplexer. Control logic connected to the first control means selects a delay through the first delay line. Control logic connected to the second control means selects a delay through the second delay line. Control logic connected to the multiplexer selects between the output of the first delay line and the second delay line.

Discrete delay line system and method

A system and method of controlling delay in a delay line. In a delay line having a system mode and an oscillator mode, wherein the delay line delays a signal as a function of a delay code, the method comprises setting the delay code, placing the delay line in oscillator mode, determining frequency of oscillation of the delay line, comparing the frequency of oscillation to a target frequency and adjusting the delay code until the frequency of oscillation of the delay line is substantially equal to the target frequency.

System and method for accurate adjustment of discrete integrated circuit delay lines

A system and method of generating a clock signal as a function of a system clock. A plurality of overlapping phases are generated and two or more of the overlapping phases are combined to form the clock signal.

System and method for generating clock signals

A method and apparatus for adjusting power supplied to a device when the device has a first and a second power input. A first voltage level and a ground potential are provided and a second voltage level is created as a function of the first voltage level. The second voltage level is then buffered with a power transistor and, if the second voltage level is needed for a particular device, the buffered second voltage level is selectively applied to the device. The circuit is disabled when the second voltage supply is not needed.

Method and apparatus for adjusting the power supply voltage provided to

A level shifting circuit which can be implemented as part of a bipolar ECL integrated circuit, provides reliable switching and level shifted output suitable for driving a low voltage CMOS integrated circuit. The circuit includes a level shifting circuit which is connected to trigger a high gain positive feedback bootstrap circuit to reliably ensure switching even under poor signal conditions. An output taken from one of the switched pair is allowed to go to V.sub.CC, 0 volts, or is clamped by a clamping circuit to -3.3 volts, representing the two output states suitable for driving inverted rail CMOS circuitry.

Bipolar ECL to inverted CMOS level translator

A circuit monitors electronic devices which require continuous clocking for non-destructive operation. The circuit samples a repetitive signal, such as a clock, from a device of interest (DOI). If, for whatever reason, the clock signal becomes absent, the circuit responds by deactivating the DOI. If the clock revives or becomes intermittent the circuit will not reactivate the DOI. The circuit will reactivate the DOI only upon application of an explicit reset signal. The circuit is all digital and therefore technology independent, and provides for precise control of the deactivation response time.

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Chippewa Falls, WI, United States of America

Mark Ronald Sikkink