International Business Machines Corporation

Mark Robert Funk

Philip Lee Vitale

Aaron Christoph Sawdey

Steven R Kunkel

Richard Karl Kirkman

Don Darrell Reed

Christopher Francois

Lynn Keat Chung

Ronald Dean Young

Randal Craig Swanberg

Vaijayanthimala K Anand

Mysore Sathyanaranyana Srinivas

Todd Jon Rosedahl

Lynn Allen McMahon

Allan E Johnson

Bruce Ralph Petz

Angela Mae Newton

Eric L Barsness

Richard D Dettinger

William Jon Schmidt

Jeffrey Douglas Brown

Kenneth Charles Vossen

Henry Joseph May

Timothy Joseph Torzewski

Daniel Guy Young

Shlomit Sarah Pinter

Jeffrey Earl Remfert

Bilha Mendelson

Mikko Herman Lipasti

Ross Evan Johnson

Scott A Hilker

Donald Arthur Morrison

Robert Carl Seemann

Thomas J Beacom

Arthur Douglas Smet

Esther Yeger-Lotem

Robert Anthony Petrillo

Gera Goft

Dimitry Kloper

Robert Ralph Roedinger

Harold E Frye

Vi Chau

Larry Keith McMains

Harold Eugene Frye

Toru Nohzawa

Christopher William Gaedke

Paul R Herrold

Travis William Haasch

Vernon R Pahl

Systems, methods and computer program products assess processor performance metrics by monitoring probes constructed using instruction sequences. A first probe value can be determined from execution of a broad spectrum probe in an execution environment. In response to determining that the first probe value is not a first expected probe value, a targeted probe providing a second probe value directed to a subsystem of the execution environment, a feature of the subsystem, or a component of the execution environment is executed. In response to determining that the second probe value is not a second expected probe value, a differential between the second probe value and the second expected probe value can be used to determine that a bottleneck exists in at least one of the subsystem of the execution environment, the feature of the subsystem, or the component of the execution environment.

Assessment of processor performance metrics by monitoring probes constructed using instruction sequences

Processor performance metrics are assessed by monitoring probes constructed using instruction sequences. A probe comprising an instruction sequence is selected. The instruction sequence can be configured to measure at least one hardware metric. A first probe value is received. The first probe value can be based, at least in part, on the hardware metric. The first probe value can be determined from execution of the probe in a first execution environment. The probe can be executed a second time to determine a second probe value. The second probe value can be based, at least in part, on the hardware metric. The second probe value is determined in a second execution environment including at least one workload. The first probe value and the second probe value can be compared to produce a performance assessment of the second execution environment.

Monitoring probes constructed using instruction sequences are used to assess processor performance metrics. A probe comprising an instruction sequence is selected. The instruction sequence can be configured to measure at least one hardware metric. A first probe value is received. The first probe value can be based, at least in part, on the hardware metric. The first probe value can be determined from execution of the probe in a first execution environment. The probe can be executed a second time to determine a second probe value. The second probe value can be based, at least in part, on the hardware metric. The second probe value is determined in a second execution environment including at least one workload. The first probe value and the second probe value can be compared to produce a performance assessment of the second execution environment.

Acceptable memory allocation for a partition is determined during and with minimal impact on normal operation of the partitioned system. The approach includes: collecting, by a processor, statistics on a rate at which pages are transferred between uncompressed and compressed memory spaces of the partition's memory; adjusting size of the uncompressed memory space; and subsequent to the adjusting, continuing with collecting of the statistics, and referencing the resultant statistics in determining an acceptable memory allocation for the partition. In one implementation, the adjusting includes stepwise decreasing size of the uncompressed memory space by reallocating uncompressed memory space to compressed memory space, and repeating the collecting of statistics for a defined measurement period for each adjusted uncompressed memory space size until performance of the partition is negatively impacted by the reallocation of uncompressed memory space to compressed memory space.

Adjusting memory allocation of a partition using compressed memory paging statistics

A computer configuration utility automatically alters system configuration parameters to sample multiple different configurations. At least one workrate metric is measured at each sampled configuration. The workrate measurements for the multiple different configurations are compared to determine the effect of different configurations with respect to at least one optimization criterion. System configuration is automatically adjusted to the optimum configuration. Preferably, the workrate metric is (non-idle) instructions executed per unit of time.

Automatic configuration sampling for managing configuration parameters of a computer system

In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.

Non-uniform memory access (NUMA) enhancements for shared logical partitions

In a logically partitioned computer system, a partition manager maintains and controls master encryption keys for the different partitions. Preferably, processes executing within a partition have no direct access to real memory, addresses in the partition's memory space being mapped to real memory by the partition manager. The partition manager maintains master keys at real memory addresses inaccessible to processes executing in the partitions. Preferably, a special hardware register stores a pointer to the current key, and is read only by a hardware crypto-engine to encrypt/decrypt data. The crypto-engine returns the encrypted/decrypted data, but does not output the key itself or its location.

Method and apparatus for protecting encryption keys in a logically partitioned computer system environment

A coprocessor performs operations on behalf of processes executing in processors coupled thereto, and accesses data operands in memory using real addresses. A process executing in a processor generates an effective address for a coprocessor request, invokes the processor's address translation mechanisms to generate a corresponding real address, and passes this real address is the coprocessor. Preferably, the real address references a block of additional real addresses, each for a respective data operand. The coprocessor uses the real address to access the data operands to perform the operation. An address context detection mechanism detects the occurrence of certain events which could alter the context of real addresses used by the coprocessor or the real addresses themselves.

Real address accessing in a coprocessor executing on behalf of an unprivileged process

Disclosed is an apparatus, method, and program product for identifying and grouping threads that have interdependent data access needs. The preferred embodiment of the present invention utilizes two different constructs to accomplish this grouping. A Memory Affinity Group (MAG) is disclosed. The MAG construct enables multiple threads to be associated with the same node without any foreknowledge of which threads will be involved in the association, and without any control over the particular node with which they are associated. A Logical Node construct is also disclosed. The Logical Node construct enables multiple threads to be associated with the same specified node without any foreknowledge of which threads will be involved in the association. While logical nodes do not explicitly identify the underlying physical nodes comprising the system, they provide a means of associating particular threads with the same node and other threads with other node(s).

Reducing remote memory accesses to shared data in a multi-nodal computer system

Multiple database queries are satisfied with the same data in a manner that assures the data is current and without having to interrogate the database for each query. In a first embodiment, all queries that are received during the processing of a first query after interrogation of the database has begun for the first query are evaluated to determine whether the result set returned for the first query will satisfy the queries received during processing of the first query. If so, the result set returned for the first query is used to generate result sets for the subsequent compatible queries received during the processing of the first query. In a second embodiment, queries are delayed and grouped, and a new query is then processed for each group that returns a result set that satisfies all of the queries in the group. In both cases, the result set for one query is used to generate a result set for a different query.

Processing database queries by returning results of a first query to subsequent queries

Mechanism for reducing remote memory accesses to shared data in a multi-nodal computer system

A packet control mechanism for a computer data system that dynamically adjusts packet training depending on the utilization load on the processor. The dynamic adjustment of packet training can be to enable and disable packet training, or adjust the number of packets in the packet train. In preferred embodiments, the computer data system includes a processor utilization mechanism that indicates a load on a processor. When the packet control mechanism determines the load on the processor is above a threshold limit, the packet control mechanism reduces the processor load by compressing the packets into the packet train. The compressing of the packets is stopped or reduced when the processor load is below a threshold in order to increase the data throughput on the network interface.

Dynamic packet training

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Mantorville, MN, United States of America

Mark Robert Funk