Lucent Technologies Inc.

At+t Corp.

At&t Bell Laboratories

Agere Systems Inc.

Agere Systems Guardian Corp.

Mark Richard Pinto

Jeffrey Devin Bude

Isik C Kizilyalli

Ya-Hong Xie

William T Lynch

Ross Alan Kohler

Ronald Lamar Freyman

Sergey Luryi

Omkaram Nalamasu

William Thomas Cochran

Joseph Rudolph Radosevich

Sheila Vaidya

Marco Mastrapasqua

Shahriar Moinian

George Patrick Watson

Nathan R Belk

Lalita Manchanda

Steven J Hillenius

Kwok K Ng

Michel Ranjit Frei

Kevin John O'Connor

David Clayton Goldthorp

Enrico Sangiori

Gerhard Hobler

Robert M Vella

Aviv Frommer

A digit signal processor capable of operating at 100 MHZ with a 1.0 volt power supply. The digital signal processor is fabricated by application of strong phase-shift lithography to obtain a 0.12 &mgr;m gate dimension. A dual-mask process is utilized to improve resolution thereby producing high speed, low-voltage processors. A n /p dual-Poly:Si module, and dopant penetration suppression techniques may be utilized.

High speed low voltage semiconductor devices and method of fabrication

An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit

A monolithically-integrated SRAM cell is described for reducing the cell size, i.e., at least two of a plurality of transistors comprising the SRAM cell are monolithically integrated to define a first transistor and a second transistor, wherein the drain of the first transistor functions as the gate of the second transistor and the drain of the second transistor functions as the gate of the first transistor. This integration eliminates the need for gate-to-drain connections of previous devices.

Monolithically-integrated static random access memory device

Logic devices of the present invention have one or more MOSFETs that are configured to operate in logic circuits, where voltages applied to the source and drain of each MOSFET are treated as logic inputs to the circuit and the resulting substrate current is treated as the logic output of the circuit. In one implementation, a MOSFET is configured in a circuit to operate as an XOR gate where a load resistor between the substrate and ground converts the substrate current into an output voltage. A sample-and-hold circuit samples and holds the output voltage to isolate the XOR gate thereby allowing DC power dissipation to be reduced. In another implementation, three MOSFETs are configured to operate as an 'ORNAND' logic device that performs the logical addition of the OR function and the NAND function.

MOSFET substrate current logic

A process for introducing negative charge onto the floating gate of an EPROM or EEPROM device is disclosed. The process uses CHISEL conditions to introduce charge onto the floating gate. The threshold voltage of the device is controlled by selecting a control gate voltage during programming that is less than 10 volts and that will provide a device with the desired threshold voltage. The device is then programmed using the selected control gate voltage and a negative substrate bias.

Method for changing electrically programmable read-only memory devices

The invention is directed to a memory cell with a floating gate and a method for charging the floating gate using channel-initiated secondary electron injection (CISEI). In the device of the present invention, a positive bias voltage of about 1.1 volts to about 3.3 volts is applied between the drain and the source when introducing charge onto the floating gate. A negative bias voltage of about -0.5 volts or more negative is applied to the substrate and the source. The drain substrate bias induces a sufficient amount of secondary hot electrons to be formed with a sufficient amount of energy to overcome the energy barrier between the substrate and the floating gate to charge the floating gate.

Method and apparatus for hot carrier injection

Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.

Planar isolation technique for integrated circuits

Disclosed are a novel logic element (designated NORAND), and articles that comprise the element. Exemplarily, the NORAND element comprises three input terminals and an output terminal. If one of the input terminals is at logic 0 then the element functions as a logic NOR unit, and if the terminal is at logic 1 the element functions as a logic AND unit. The novel element thus makes possible reprogrammable and/or self-organizing logic circuits. The NORAND element can be realized with a single active semiconductor device, exemplarily a real space transfer (RST) device.

Logic element and article comprising the element

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Summit, NJ, United States of America

Mark Richard Pinto