International Business Machines Corporation

Advanced Micro Devices Corporation

Mark Richard Nutter

Barry L Minor

Maximino Aguilar, Jr

Michael Norman Day

Charles Ray Johns

Brian King Flachs

James Michael Stafford

Daniel Alan Brokenshire

Kathryn Mary O'Brien

Tong Chen

Brad William Michael

Tao Zhang

John K P O'Brien

Alexandre E Eichenberger

Ching-Yung Lin

James Xenidis

Toyotaro Suzumura

Ilie G Tanase

Jason L Crawford

Jie Lu

Danny L Yeh

Chun-Fu Chen

Gordon Clyde Fossum

Joaquin Madruga

VanDung Dang To

Harm Peter Hofstee

John Kevin Patrick O'Brien

Michael Stan Gowen

Gabriel H Loh

Michael Ignatowski

Mitesh Ramesh Meswani

Kanna Shimizu

David Andrew Roberts

Catherine Helen Crawford

Kevin J Gildea

Alex Chunghen Chow

John Robert Slice

Michael K Gschwind

Mauricio Breternitz, Jr

Ulrich Weigand

Thuong Quang Truong

Sergey Blagodurov

Daniel Lawrence Stasiak

George Francis Ramsay, Iii

Dean J Burdick

Ayal Zaks

Mark Henry Oskin

Roy Moonseuk Kim

Sidney James Manning

Robert Paul Stelzer

Yasukichi Okawa

Wei Kuo

Debra A Kipping

Truc Duy Nguyen

Prashant Jayaprakash Nair

Revital Erez

Maximino Jr Aguilar

A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.

Distributed graph databases that facilitate streaming data insertion and queries by efficient throughput edge addition

Distributed graph databases that facilitate streaming data insertion and queries by reducing number of messages required to add a new edge by employing asynchronous communication

Distributed graph databases that facilitate streaming data insertion and low latency graph queries

A method and system of storing and retrieving data in a computer system are disclosed. In an embodiment, the method comprises storing a data object at a specified location in a first data store, storing in a second data store first information identifying said specified location, retrieving the data object from a defined location in the first data store, obtaining second information identifying the defined location in the first data store, and comparing the second information to the first information to determine if the first information and the second information identify a same location in the first data store. In embodiments of the invention, the method further comprises when the second information and the first information identify different locations in the first data store, generating a fault signal to indicate that the location of the data object in the first data store has changed.

Distributed client based cache for keys using demand fault invalidation

Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

Arranging binary code based on call graph partitioning

A processor modifies memory management mode for a range of memory locations of a multilevel memory hierarchy based on changes in an application phase of an application executing at a processor. The processor monitors the application phase (e.g., computation-bound phase, input/output phase, or memory access phase) of the executing application and in response to a change in phase consults a management policy to identify a memory management mode. The processor automatically reconfigures a memory controller and other modules so that a range of memory locations of the multilevel memory hierarchy are managed according to the identified memory management mode. By changing the memory management mode for the range of memory locations according to the application phase, the processor improves processing efficiency and flexibility.

Techniques for changing management modes of multilevel memory hierarchy

A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.

Memory page access detection

Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor. Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.

Parallel execution unit that extracts data parallelism at runtime

Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor, Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.

Growing community of inventors

Austin, TX, United States of America

Mark Richard Nutter