Opti, Inc.

Broadcom Corporation

Other

Mark R Williams

Sukalpa Biswas

Robert S French

Ian Eslick

Jay Li

Kelly Gene Johnson

John R Nickolls

Scott David Johnson

Lawrence John Madar, Iii

Ethan A Mirsky

Loi Van Tran

Dipankar Bhattacharya

Michael Schumacher

Kambdur Kirthiranjan

Amrit Raj Pant

Methods and apparatuses whereby legally obtained media files are marked so they are associated with the legal owner. A legally obtained media file is delivered normally, without any form of interruption. However, when an illegally obtained media file is delivered, a message file is delivered in association with the media file. According to an embodiment, a method of the invention comprises receiving a media file, retrieving an identifier that uniquely identifies a player unit, appending the identifier onto the media file, and storing the appended media file in a data storage medium. According to another embodiment, a method of the invention comprises receiving a media file with a first identifier, retrieving a second identifier, comparing the first identifier with the second identifier, retrieving a message file from a non-volatile memory and producing a message output if the first identifier does not correspond to the second identifier, and producing a media output from the media file.

Methods and apparatuses for media file delivery

A method and system for debugging an executing service on a pipelined CPU architecture are described. In one embodiment, a breakpoint within an executing service is set and a minimum state of the executing service is saved. In addition, a program counter of the executing service is altered. The program counter is restored and the state of the executing service is restored.

Multi-channel, multi-service debug on a pipelined CPU architecture

An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.

Compact ISA-bus interface

A system and method for executing previously created run time executables in a configurable processing element array is disclosed. In one embodiment, this system and method begins by identifying at least one subset of program code. The method may then generate at least one set of configuration memory contexts that replaces each of the at least one subsets of program code, the at least one set of configuration memory contexts emulating the at least one subset of program code. The method may then manipulate the at least one set of multiple context processing elements using the at least one set of configuration memory contexts. The method may then execute the plurality of threads of program code using the at least one set of multiple context processing elements.

System and method for executing hybridized code on a dynamically configurable hardware environment

A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed. For each vector, vector address units provide addresses which stride through each element of each vector.

Reconfigurable processing system and method

A system and method for executing previously created run time executables in a configurable processing element array is disclosed. In one embodiment, this system and method begins by identifying at least one subset of program code. The method may then generate at least one set of configuration memory contexts that replaces each of the at least one subsets of program code, the at least one set of configuration memory contexts emulating the at least one subset of program code. The method may then manipulate the the at least one set of multiple context processing elements using the at least one set of configuration memory contexts. The method may then execute the plurality of threads of program code using the at least one set of multiple context processing elements.

A system and method for emulating a USB peripheral device is disclosed. The system utilizes a USB programming and operating interface to interact with the host but formats the data into a format usable by a non-USB peripheral device. Such a system consumes less real estate and power than a USB interface controller and USB peripheral, but remains compatible with software designed to interact with those USB devices.

USB data serializer

A system in accordance with the invention provides a chipset for use generally in a PC-type system and that includes a plurality of programmable I/O (PIO) pins. Each of the PIO pins can be programmed to carry signals in accordance with any function in a function pool. In one embodiment, the number of PIO pins total 32 and the number of functions total 70. Such programmability allows a single-chip chipset to be vendor platform-generic while simultaneously minimizing pin count.

System and method of pin programming and configuration

A temperature sensing apparatus is disclosed which generates a signal having a frequency which is related to temperature. The apparatus includes means for receiving a temperature input, an output for carrying an output signal having a frequency related to the temperature output, and a converting means for converting the temperature input to the output signal.

Method and apparatus for temperature sensing

A system and method in accordance with the invention permits the full support of two ISA buses, a local ISA bus and a second ISA bus. To do so, upon receiving an access cycle, the cycle is directed to the second ISA bus. The second ISA bus is monitored for a signal event which indicates that an ISA device is claiming the cycle. If the signal event does not occur, the cycle is directed to the local ISA bus.

System and method of positively determining ISA cycle claiming

A system and method in accordance with the invention allows the emulation of a DMA transfer between a device such as a CD-ROM which is incapable of a bus-mastering mode of operation (e.g., a DMA transfer) and a memory. Following receipt of an interrupt request, a system in accordance with the invention generates an I/O access cycle to the device, retrieves data and stores the data in a buffer. Following data retrieval, the system transfers the data to host memory. Once data is transferred to host memory, an interrupt is generated to the host processor. Thus, host processor resources are not required to perform a data transfer with devices unable to become bus-masters.

System and method for bus master emulation

A system in accordance with the invention comprises a first clock input for carrying a clock input signal having first clock cycles, a clock output for carrying an output clock signal having cycles which are synchronous with the first clock cycles, and programmable delay means. Programmable delay means receives the clock input signal, and generates the output clock signal which is delayed from the input by at least a programmable delay and where the programmable delay causes the output clock signal to be synchronous with the input clock signal.

Growing community of inventors

San Jose, CA, United States of America

Mark R Williams