Intel Corporation

Mark R Waggoner

Robert J Greiner

Mark J Balmer

David Lawrence Hill

Tim Frodsham

Anant S Deval

Derek T Bachand

Matthew W Heath

Brett W Newkirk

In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.

Communicating via an in-die interconnect

A detector to detect the magnitude of the jitter that may occur in a first clock signal and a second clock signal and to generate an alarm signal if the magnitude of the jitter exceeds the threshold value. The detector comprises a one-hot register storing a one-hot value comprising a first logic bit (=1) centered around one or more second logic bits (=0). The detector comprises a threshold register storing a threshold value comprising one or more second logic bits centered around one or more first logic bits. An event of a first clock rotates the contents of the one-hot value and an event of a second clock rotates the contents of the threshold value. A match between the pre-specified bit of the one-hot value and the threshold value indicates the occurrence of the jitter having a magnitude greater than the threshold value.

Clock jitter detector

A method and apparatus for providing programmable self-testing in a memory. Registers in the memory are programmed with a sequence of instructions for performing the self-test of the memory. The sequence of instructions is run to perform the self-test of the memory, and the results are checked. The memory includes a clock multiplier which allows the registers to be programmed at a first clock rate, then the memory is tested at a second clock rate which is faster than the first clock rate.

Programmable built-in self-test function for an integrated circuit

A computer system includes a microprocessor and an external cache memory coupled to the microprocessor. The cache memory includes a memory array and an apparatus for initiating a routine to test the integrity of the memory array in response to a signal asserted by the microprocessor. The apparatus generates a two-bit status signal coupled to the microprocessor for communicating IDLE, ACTIVE, PASS and FAIL states of the test routine. The apparatus initiates the test routine a predetermined of number clock cycles after the assertion of the signal provided by the microprocessor.

Growing community of inventors

Hillsboro, OR, United States of America

Mark R Waggoner