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Micron Technology Incorporated

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Mark R Visokay

Luigi Colombo

James Joseph Chambers

Antonio L P Rotondaro

Gurtej S Sandhu

Cem Basceri

Howard E Rhodes

Scott Robert Summerfelt

Dan Gealy

Antonio Luis Pacheco Rotondaro

Garo Jacques Derderian

Haowen Bu

Guoqiang Xing

Thomas M Graettinger

Weimin Li

Rajesh B Khamankar

Theodore Sidney Moise

Francis Gabriel Celii

Stephen Roy Gilbert

Justin F Gaynor

Haining Yang

Steven D Cummings

Vishnu Kumar Agarwal

Sam Yang

John M Drynan

Douglas E Mercer

Tom Graettinger

Steve Cummings

Shaofeng Yu

Shashank Sureshchandra Ekbote

Paul C McIntyre

Borna J Obradovic

Manuel A Quevedo-Lopez

Robert William Murto

Zhengwen O Li

Mahalingam Nandakumar

William David French

Bhaskar Srinivasan

Jiong-Ping Lu

Richard L Guldi

Freidoon Mehrad

Ricky A Jackson

Dok Won Lee

Yaw S Obeng

Oh-Jung Kwon

Brian Goodlin

Lindsey H Hall

Husam N Alshareef

Tae S Kim

Malcolm John Bevan

Erika Lynn Mazotti

Dirk N Anderson

Michael Francis Pas

Yuanning Chen

Gregory Boyd Shinn

Jorge Adrian Kittl

Poornika Fernandes

John Paul Campbell

Manfred Ramin

Wai Lee

Narasimhulu Kanike

Clint Montgomery

Mark A Kressley

Aaron L Frank

David Gonzalez, Jr

Bo-Yang Lin

Eric D Rullan

Sung-Jen Fang

Yen Lee

Sagnik Dey

Glenn A Cerny

Antonio LP Rotondaro

An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

IC with 3D metal-insulator-metal capacitor

Various examples provide an electronic device that includes first and second resistor segments. Each of the resistor segments has a respective doped resistive region formed in a semiconductor substrate. The resistor segments are connected between first and second terminals. The first resistor segment is configured to conduct a current in a first direction, and the second resistor segment is configured to conduct the current in a second different direction. The directions may be orthogonal crystallographic directions of the semiconductor substrate.

Trimmable silicon-based thermistor with reduced stress dependence

A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.

Dummy contacts to mitigate plasma charging damage to gate dielectrics

Multi-step deposition of lead-zirconium-titanate (PZT) ferroelectric material. An initial portion of the PZT material is deposited by metalorganic chemical vapor deposition (MOCVD) at a low deposition rate, for example at a temperature below about 640 deg C. from vaporized liquid precursors of lead, zirconium, and titanium, and a solvent at a collective flow rate below about 1.1 ml/min, in combination with an oxidizing gas. Following deposition of the PZT material at the low flow rate, the remainder of the PZT film is deposited at a high deposition rate, attained by changing one or more of precursor and solvent flow rate, oxygen concentration in the oxidizing gas, A/B ratio of the precursors, temperature, and the like.

Multi-step deposition of ferroelectric dielectric material

An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH) and nitrogen (N) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350&#xb0; C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N&#x2014;H bonds rather than Si&#x2014;H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.

Hydrogen-blocking film for ferroelectric capacitors

The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.

Semiconductor device fabricated using a metal microstructure control process

A shallow trench isolation structure is formed in a semiconductor substrate adjacent to an active semiconductor region. A selective self-assembling oxygen barrier layer is formed on the surface of the shallow trench isolation structure that includes a dielectric oxide material. The formation of the selective self-assembling oxygen barrier layer is selective in that it is not formed on the surface the active semiconductor region having a semiconductor surface. The selective self-assembling oxygen barrier layer is a self-assembled monomer layer of a chemical which is a derivative of alkylsilanes including at least one alkylene moiety. The silicon containing portion of the chemical forms polysiloxane, which is bonded to surface silanol groups via Si&#x2014;O&#x2014;Si bonds. The monolayer of the chemical is the selective self-assembling oxygen barrier layer that prevents diffusion of oxygen to a high dielectric constant material layer that is subsequently deposited as a gate dielectric.

Selectively self-assembling oxygen diffusion barrier

Example embodiments provide triple-gate semiconductor devices isolated by reverse shallow trench isolation (STI) structures and methods for their manufacture. In an example process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The example triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.

Triple-gate transistor with reverse shallow trench isolation

A method includes providing a substrate having insulating layers thereon; forming a first trench in a first region of the substrate and a second trench in a second region of the substrate; thermally growing layers of oxide along the sides of the trenches; filling the first trench and the second trench with a polysilicon material, planarizing the polysilicon material, and creating a shallow trench isolation between the first region and the second region, wherein the step f) of creating the shallow trench isolation is performed only after the steps of d) filling and e) planarizing.

Method of fabricating an embedded polysilicon resistor and an embedded eFuse isolated from a substrate

A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.

Method to attain low defectivity fully silicided gates

The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate (). This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure (), wherein the NMOS gate structure () includes an NMOS gate dielectric () and an NMOS gate electrode (). This method further includes forming n-type source/drain regions () within the substrate () proximate the NMOS gate structure (), and siliciding the NMOS gate electrode () to form a silicided gate electrode (). This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode () prior to or concurrently with siliciding.

Use of dopants to provide low defect gate full silicidation

A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

Gate structure and method

One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.

Methods for full gate silicidation of metal gate structures

Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.

Dual work function CMOS devices utilizing carbide based electrodes

Growing community of inventors

Dallas, TX, United States of America

Mark R Visokay