Micron Technology Incorporated

Rambus Inc.

Micron Semiconductor, Inc.

Mark R Thomann

Wen Qian Li

Huy Thanh Vo

Glen F Hush

Glen Earl Hush

Charles L Ingalls

Adrian E Ong

Daniel R Loughmiller

Nick Van Heel

Paul Fuller

Scott E Schaefer

Jeff Mailloux

Mike Seibert

Timothy B Cowles

Mirmajid Seyyedy

Christopher K Morzano

William F Jones

Paul M Fuller

Terry R Lee

Methods, systems, and apparatus for testing semiconductor devices.

Testing fuse configurations in semiconductor devices

A system includes a first integrated circuit configured to operate in at least a normal mode and a test mode and a second integrated circuit, where both the first integrated circuit and the second integrated circuit are disposed within a same semiconductor device package. The system further includes a first terminal, external to the semiconductor device package, electronically coupled to the first integrated circuit and the second integrated circuit. The first terminal is electronically coupled to a buffer in the second integrated circuit and used to convey signals to or from the first integrated circuit.

Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.

A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data is written to cells in a memory device, the cells are read to generate read data, the read data is compressed to generate test data, and the test data is produced at a single output on edges of a clock signal.

Method and apparatus for testing a memory device with compressed data using a single output

Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

Double data rate scheme for data output

A memory device includes delay locked loop that generates an internal signal based on an external signal. The internal signal serves a reference clock signal for most modes operations of the memory device. In a self refresh mode, the delay locked loop is completely deactivated to completely deactivate the internal signal. In a non-self refresh mode, the delay locked loop is periodically deactivated to periodically deactivate the internal signal based on certain modes of operations of the memory device.

Delay locked loop control circuit

A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.

Controller for delay locked loop circuits

An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

Method of reducing standby current during power down mode

A number of embodiments of memory devices and methods of performing read/write timing calibration of these memory devices using a row or a redundant row. Addressing of the row or redundant row in a memory array of a memory device may be accomplished by using a calibration fuse bank to address a row or a redundant row of the memory array, by using a fuse bank of the memory device to address a redundant row of the memory array, or by storing the row address of a row in a memory controller and providing the row address to the memory device during calibration. A redundant row used for calibration may be a redundant row not utilized by a memory device during repair of its memory array. A row used for calibration may be a row not utilized by a memory device due to the nature of the specific application in which that memory device is being used. A unique data pattern may then be written to and read from the addressed row or redundant row for read/write timing calibration. Use of a nonutilized row or redundant row for read/write timing calibration according to the present invention enables calibration to be performed during operation of a memory device without compromising data integrity.

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Boise, ID, United States of America

Mark R Thomann