Sun Microsystems, Inc.

Micro Magic, Inc.

Mark R Santoro

Lee S Tavrow

Gary W Bewick

Robert J Bosnyak

David M Murata

Robert J Drost

Randon Wayne Smith

A programmable logic array (PLA) AND plane receives data input signals from input registers and generates corresponding minterms. The minterms are OR-ed together to form a sum of products, which are provided to output latches and clocked out before the end of each clock cycle by an internal self-timed signal as PLA output data. The OR plane (or the AND plane, or both) includes NOR gates that include a plurality of NMOS transistors. Each NMOS transistor in a gate has its drain connected to a common NOR gate output node, its source connected to ground and its gate connected to receive a corresponding minterm from the AND plane. The NOR gate further includes a PMOS load transistor having its source connected to a voltage supply, its drain connected to the NOR gate output node and its gate connected to receive a timing signal that turns on the PMOS load transistor as the minterms are generated at the output of the AND plane and turns off the PMOS load transistor when the sum of products are provided at the output latches.

Controlled PMOS load on a CMOS PLA

The speed of large SRAMs is improved by embedding sense amplifiers into the SRAM core. In this way, the bit line length that the SRAM cells must drive is very short and, thus, the slew rate is fast. An additional layer of metal is employed to route and accumulate the sense amp results vertically over the entire SRAM core. To reduce the required pitch of the additional metal layers, a sense amp muxing scheme is also provided.

Fast SRAM design using embedded sense amps

A phase locked loop (PLL) circuit includes a phase comparator that compares the phases of an input signal and a feedback signal and generates UP and DOWN pulses that are related to the phase difference. A charge pump receives the UP and DOWN pulses from the phase comparator and either charges or discharges the tuning voltage of a loop filter. The voltage controlled oscillator (VCO) provides an output signal that has a frequency that is related to the tuning voltage. A frequency divider then divides the frequency of the VCO output by a factor of N and provides the output as the feedback signal to the phase comparator. The PLL includes pre-lock circuitry that responds to an active state of a pre-lock input signal by narrowing the dynamic range of the VCO to a pre-lock range that is centered around a predetermined final frequency and that deactivates upon achieving the pre-lock range.

Automatically adjusting the dynamic range of the VCO in a PLL at

An integrated circuit memory structure includes a plurality of regular columns of memory cells arranged as a sequence such that each regular column except the last in the sequence has an associated adjacent regular column. Each regular column has associated sense amplifier circuitry and write driver circuitry for, respectively, reading output data from and writing input data to the regular column. At least one redundant column of memory cells is also provided. The structure also includes a programmable element that responds to a programming stimulus by providing a programming signal that identifies one of the regular columns as a defective column. Reconfiguration circuitry responds to the programming signal by reconfiguring the memory structure such that the sense amplifier circuitry and the write driver circuitry of each regular column in the sequence, beginning with the defective column, is reconfigured to be associated with the adjacent regular column. The sense amplifier circuitry associated with the last regular column in the sequence is reconfigured to be associated with the redundant column, which has its own associated write driver. The concepts of column redundancy are also applicable to row redundancy.

Redundancy scheme for semiconductor RAMS

An improved approach for breaking the bit lines of a semiconductor memory device into small pieces, referred to herein as Embedded Access Trees (EATs), is introduced. Embedded Access Trees enjoy the principal advantage of the banked approach by dividing long bit lines into several smaller bit lines to decrease the effective load which a selected cell must drive. However, EATs avoid most of the limitations of the banked approach, e.g., increased size, power and complexity. In a preferred embodiment of the invention, EATs are embedded into the existing full array and do not require additional peripheral decoders, MUXes or complex and costly global routing. For a given processing technology, the present invention permits a full memory array to be subdivided into more subarrays than the banked approach, with corresponding performance improvements.

Embedded access trees for memory arrays

An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability. In this embodiment, each output driver includes a CMOS inverter pair and a bipolar transistor coupled between the respective output node of the driver and V.sub.DD.

ECL to CMOS converter

A circuit for detecting multiple address matches in an associative array includes a match current generator that responds to active match signals generated by the associative array by generating a match current that is linearly proportional to the number of active match signals generated by the array. A reference current source generates a reference current that is between one and two times greater than the match current when a single active match signal is generated by the associative array. A comparator compares the match current and the reference current and generates an active output signal when the match current is greater than the reference current.

Method and appartus for detecting multiple address matches in a content

A row select circuit for semiconductor memories is disclosed. The row select circuit includes a decoder portion and a driver portion. The decoder potion of the row select circuit includes a plurality of decoder circuits, each servicing a multiplicity of rows. Two levels of decoding are used to select a row. First, one of the plurality of decoder circuits is selected. Second, a predecoder is provided for simultaneously selecting one of the multiplicity of rows serviced by the selected decoder circuit. A single current source is used to service the multiplicity of rows associated with a particular decoder. The driver portion of the circuit includes a driver circuit for each row. Each driver includes an inverter stage, a driver stage, a clamp and a voltage reference circuit. For a selected row, the driver circuit provides ultra-fast access time. For the deselected rows, the driver circuit consumes minimal power.

Word line decoder/driver circuit and method

A driver circuit for use in a semiconductor memory array is disclosed. The memory array includes a plurality of the driver circuits, each used to drive a word line in the memory array. The driver circuit of the present invention includes a pull up portion and an active pull down portion. The pull up portion includes a pair of cascaded transistors arranged to pull up an output node coupled to the word line. The active pull down portion includes a pair of cascaded transistors arranged to pull down the output node coupled to the word line. A control feedback path is coupled between the output node and the active pull down portion of the driver circuit. The feedback path controls the activation of the pull down portion of the driver circuit.

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Sunnyvale, CA, United States of America

Mark R Santoro