International Business Machines Corporation

Mark R LaForce

Charles Hampton Perry

Paul M Gaschke

Roger R Schmidt

Dennis R Barringer

David Lewis Gardell

Wade H White

James N Humenik

Santiago E Del Puerto

Donald W Porter

Daniel George Berger

Marc Douglas Knox

Suryanarayan G Hegde

Dale Curtis McHerron

Dennis R Conti

James M Crafts

Mark Anthony Marnell

Joseph J Van Horn

Anthony J Abrami

Frederick L Taber, Jr

Thomas W Bachelder

Stuart H Bullard

Paul J Roggemann

Kort F Longenbach

Gobina Das

John A Fredeman

A socket for testing or burning-in electronic components has a cover including a heat sink and a sensor. The heat sink and sensor are spring loaded so they make direct, temporary contact to an electronic component in the socket during burn-in. A heat transferring device is coupled to each heat sink. The heat transferring device uses input from the sensor to provide heat or cooling to each heat sink to individually control the temperature of each component. The heat transferring device can be an electric heater or a cooling device, such as a fan. Both can also be used. A plurality of these sockets are used in a forced air convective oven for burning-in a plurality of electronic components at one time. The oven provides oven heating and cooling for all components while the socket heater and sensor provide individual temperature control for each component.

Actively controlled heat sink for convective burn-in oven

An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation. Evacuation also provides atmospheric pressure augmentation of contact for connection between boards and contact to wafer. Probes for parallel testing of chips are arranged in crescent shaped stripes to significantly increase tester throughput as compared with probes arranged in an area array.

Segmented architecture for wafer test and burn-in

A fixture to hold an electronic substrate having probe areas on a top surface. The top surface of the electronic substrate is left open to provide a maximum area to couple interconnect wires for a device under test. In addition, a bottom surface of the substrate is left open to provide a maximum area to couple with a probe card in one embodiment, or a test head in another embodiment. This open bottom and open top minimize the mechanical interference with electrical connections. The substrate is planarized to a frame by one or more clamps that are attached to the frame. The clamps provide adjustment of the pressure down on the substrate in a Z-axis direction which is normal to the top surface of the substrate for providing a good connection with a planar card. In addition, the clamps provide adjustment in the an X-Y plane parallel to the frame and rotational correction about the Z-axis.

Mechanical fixture for holding electronic devices under test showing adjustments in multiple degrees of freedom

A plurality of multilayer glass-ceramic substrates are arranged in coplanar relationship in a tile pattern within a support platform. The glass-ceramic substrates and the support platform are both formed of materials having thermal expansion characteristics substantially equal to that of a wafer which is supported by the coplanarly aligned substrates during test and burn-in of the wafer. The present invention effectively solves the problem of providing a single large support member for wafer test and burn-in, which heretofore have been limited in mechanical properties and power capability.

Wafer test and burn-in platform using ceramic tile supports

A multiple-chip probe assembly suitable for wafer testing over a wide temperature range includes a plurality of individual buckling beam probe elements. A support structure supports the plurality of buckling beam probe elements in an arrangement in accordance with an electrical contact footprint for use in electrically contacting multiple chips of a wafer under test and enables buckling movement in a contacting direction of the plurality of buckling beams. The support structure includes a principal support material having a thermal coefficient of expansion (TCE) matched with the wafer under test and a second material other than the principal support material, wherein a contact positioning of the plurality of buckling beam probe elements upon the wafer under test during a testing operation is maintained. The second material prevents an individual probe element from electrically contacting the principal support material.

Large area multiple-chip probe assembly and method of making the same

A wafer chuck temperature control system is disclosed for use in a semiconductor wafer testing apparatus. The wafer chuck is divided into a plurality of temperature sensor and cooling element domains corresponding to chip location regions of an overlying undiced wafer being tested. Computer scanning of the sensors determines which domain is the one harboring the heat source (chip under test) and selects the same for connection to a closed loop temperature control feedback servo. Provision also is made for introducing a helium gas interface between the wafer and the chuck by placing annular grooves in the face of the chuck through which the helium flows when the wafer is vacuum-seated against the chuck. A predetermined helium gas flow rate is maintained to preserve vacuum holddown and to optimize the thermal resistance of the wafer-chuck interface.

Dry interface thermal chuck temperature control system for semiconductor

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Essex Junction, VT, United States of America

Mark R LaForce