Sun Microsystems, Inc.

Oracle International Corporation

Oracle America, Inc.

The University of British Columbia

Mark R Greenstreet

Tarik Ono

Suwen Yang

Robert J Drost

Robert J Bosnyak

Josephus Ebergen

Alex Chow

William Stuart Coates

Ian W Jones

Stuart Alexander Ridgway

Brian Winters

Hetal N Gaywala

A source-synchronization interface circuit includes: a sender synchronous-to-asynchronous protocol converter that receives sender data and a sender clock and that has regenerative gain to resolve metastability during phase synchronization of the sender clock and a receiver clock; an asynchronous FIFO buffer with multiple stages that conveys phase information and data from the sender synchronous-to-asynchronous protocol converter to a receiver synchronous-to-asynchronous protocol converter; and a receiver synchronous-to-asynchronous protocol converter that receives the receiver clock and that has regenerative gain to resolve metastability during the phase synchronization. Moreover, the source-synchronization interface circuit includes control logic that initializes the source-synchronization interface circuit by operating the stages in the asynchronous FIFO buffer in a slow mode having a cycle time less than a data-transfer period for a predetermined number of clock cycles, and subsequently operating the stages in a normal mode having a cycle time that is less than that for the slow mode.

Deskew FIFO buffer with simplified initialization

A clock deskew circuit for transferring data from a first clock domain to a second clock domain. This circuit includes a data path, which has: a transmitter latch controlled by a transmitter clock in a first clock domain; a receiver latch controlled by a receiver clock in a second clock domain; and an intermediate latch coupled between the transmitter latch and the receiver latch. The transmitter clock and the receiver clock have an unknown phase offset. The circuit additionally includes a control circuit coupled between the transmitter clock and the receiver clock, and generates a control clock for the immediate latch based on the transmitter clock and the receiver clock. The control circuit selects between a first operation mode and a second operation mode for the data path circuit based at least on the phase relationship of the control clock with respect to the transmitter clock and the receiver clock.

Flip-flop-based clock deskew circuit

The disclosed embodiments provide a system that filters pre-fetch requests to reduce pre-fetching overhead. During operation, the system executes an instruction that involves a memory reference that is directed to a cache line in a cache. Upon determining that the memory reference will miss in the cache, the system determines whether the instruction frequently leads to cache misses. If so, the system issues a pre-fetch request for one or more additional cache lines. Otherwise, no pre-fetch request is sent. Filtering pre-fetch requests based on instructions' likelihood to miss reduces pre-fetching overhead while preserving the performance benefits of pre-fetching.

Filtering pre-fetch requests to reduce pre-fetching overhead

The disclosed embodiments provide a system that uses speculative cache requests to reduce cache miss delays for a cache in a multi-level memory hierarchy. During operation, the system receives a memory reference which is directed to a cache line in the cache. Next, while determining whether the cache line is available in the cache, the system determines whether the memory reference is likely to miss in the cache, and if so, simultaneously sends a speculative request for the cache line to a lower level of the multi-level memory hierarchy.

Using speculative cache requests to reduce cache miss delays

The disclosed embodiments provide a synchronization circuit that supports multiple parallel reads and writes. This synchronization circuit includes multiple coupled data storage locations that synchronize data and control signals between two time domains and control logic that facilitates simultaneously accessing a variable number of such data storage locations in the same clock cycle. During operation, the synchronization circuit receives a request to simultaneously access (e.g., read and/or write) two or more synchronized data storage locations. In response to the request, the control logic in the synchronization circuit determines whether the present state of the synchronization circuit can accommodate the request, and if so, simultaneously accesses two or more synchronized data storage locations.

Synchronization circuit that facilitates multiple parallel reads and writes

Embodiments of a synchronization circuit are described. This synchronization circuit includes multiple selectively coupled synchronization stages which are configurable to synchronize data and control signals between a first time domain and a second time domain, where the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain. Additionally, the synchronization circuit includes control logic, coupled to the synchronization stages, which is configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during the synchronization.

Adaptive synchronization circuit

The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.

Synchronizer latch circuit that facilitates resolving metastability

An interconnect for surfing circuits is presented. The interconnect includes at least one control signal line, at least one data signal line, and at least one variable capacitor coupled to the at least one control signal line and the at least one data signal line, wherein the capacitance of the variable capacitor is configured to be controlled by a control signal on the control signal line so that a velocity of a data signal transmitted on the at least one data signal line is determined by the value of the capacitance of the variable capacitor.

Interconnect for surfing circuits

The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The present invention seeks to reduce EMI emissions by phase-modulating the clock signal using tunable delay lines. Phase modulation causes a spreading of the energy spectrum of the clock signal thereby reducing EMI emissions. In addition, the present invention is capable of generating a wide energy spectrum in a short time interval. Furthermore, the present invention can be similarly applied to other signals which exhibit a periodic or timing nature due to a correlation with the clock signal.

EMI reduction using tunable delay lines

One embodiment of the present invention provides a system that provides skew compensation for communications across a source-synchronous self-timed network. During each clock period, the system allows multiple synchronous transmitters to each transmit one data element and to assert one acknowledgement on a transmit clock line into the self-timed network. In doing so, the multiple synchronous transmitters do not wait for requests from the self-timed network before transmitting a subsequent data element. Similarly, during each clock period, the system allows multiple synchronous receivers to accept one data element from and to assert one request on a receive clock line coupled into the self-timed network. In doing so, the multiple synchronous receivers do not wait for acknowledgments from the self-timed network before receiving a subsequent data element. The self-timed network is configured to tolerate bounded skew between the multiple synchronous transmitters and multiple synchronous receivers.

Method and apparatus for providing skew compensation using a self-timed source-synchronous network

The clock signal is the dominant source of electromagnetic interference (EMI) for many electronic devices. EMI generated by an electronic device must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. EMI emissions are reduced by phase-modulating the clock signal using tunable delay lines. Phase modulation causes a spreading of the energy spectrum of the clock signal thereby reducing EMI emissions. Implementations of the tunable delay lines are provided. In one implementation, a tunable delay line includes a first pipeline, a second pipeline, and a coupling mechanism for coupling the first pipeline to the second pipeline at various transfer points. The forward latency of the second pipeline is longer than that of the first pipeline. Based on external control signals, a clock pulse traveling along the first pipeline can be transferred via the coupling mechanism to the second pipeline thereby allowing the clock pulse to continue to propagate along the second pipeline.

System for controlling a tunable delay by transferring a signal from a first plurality of points along a first propagating circuit to a second plurality of points along a second propagating circuit

A surfing pipelined logic circuit has a timing system which provides a timing signal sequentially to each of a plurality of logic blocks. The logic blocks are connected in a series and may have a linear configuration or a ring configuration. Each of the logic blocks has a latency which is variable in response to the timing signal. When the timing signal is not present, the latency is longer than a timing delay which occurs between the timing system applying the timing signal to the logic block and the timing signal applying the logic signal to a next one of the logic blocks. When the timing signal is present, the latency is shorter than the timing delay. The timing system may comprise a timing path carrying timing signals. The timing path may have a number of nodes connected to control inputs of corresponding ones of the logic blocks.

Surfing logic pipelines

One embodiment of the present invention provides a system that transmits a stream of datawords through a bundle of conductors with a three-dimensional structure. Upon receiving a dataword to be transmitted, the system uses an encoding function to encode the dataword into a current codeword in a stream of codewords, wherein the current codeword is less than double the size of the dataword. Next, the system transmits the current codeword to a destination through the bundle of conductors. Note that the encoding function depends on a preceding codeword in the stream of codewords, so that when the preceding codeword changes to the current codeword, rising transitions are substantially matched with falling transitions within the bundle.

Method and apparatus for facilitating balanced bundles of electrical signals

The present invention provides a method and apparatus for data flow control. One embodiment detects input congestion and output starvation in a plurality of sub-buffers of a ripple FIFO buffer. This embodiment is used to draw conclusions about the occupancy of the ripple FIFO buffer under steady-state conditions. One embodiment detects input congestion and output starvation at every sub-buffer of the ripple FIFO buffer. Other embodiments detect input congestion and output starvation at a subset of the sub-buffers of the ripple FIFO buffer. One embodiment determines occupancy of the ripple FIFO buffer by the number of sub-buffers which report a steady congested state. Another embodiment determines occupancy of the ripple FIFO buffer by the number of sub-buffers which report a steady starved state. Another embodiment determines occupancy of the ripple FIFO buffer by the location of sub-buffers which report a steady congested state. Another embodiment determines occupancy of the ripple FIFO buffer by the location of sub-buffers which report a steady starved state. Other embodiments determine occupancy of the ripple FIFO buffer by a combination of the above methods.

Method and apparatus for data flow analysis

One embodiment of the present invention provides a system that keeps track of transitions on signal lines in order to latch a dataword in a stream of datawords. This stream of datawords is generated so that each transition between successive datawords involves a minimum number of transitions on a set of signal lines. During operation, the system monitors the set of signal lines that carries the stream of datawords. Upon detecting a predetermined number of transitions on the set of signal lines, the system waits a fixed time interval to ensure that a dataword is ready to be latched, and then latches the dataword.

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Vancouver, Canada

Mark R Greenstreet