Nvidia Corporation

Mark R Goudy

Dominic Acocella

Andrew J Tao

Methods, apparatuses, and systems are presented for performing multiple concurrent accesses in a shared memory resource comprising storing a first group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the first group being stored in a data entry in a first bank; skipping at least one data entry in at least one bank after storing a last data element of the first group, to introduce an offset; following the offset, storing a second group of data elements in data entries across multiple banks in the shared memory resource, a first data element of the second group being stored in a data entry in a second bank different from the first bank; and concurrently accessing the first data element of the first group from the first bank and the first data element of the second group from the second bank.

Concurrent access of data elements stored across multiple banks in a shared memory resource

An output buffer in a multi-threaded processor is managed to store a variable amount of output data. Parallel threads produce a variable amount of output data. A controller is configured to determine how much output buffer space is needed per thread and how many threads can execute in parallel, given the available space in the output buffer. The controller also determines where each thread writes to in the output buffer.

Configurable output buffer ganging for a parallel processor

A circular buffer having an active cache window can be configured to temporarily allocate one or more locations in the active cache as permanent memory locations to eliminate the possibility of overwriting the contents of the permanent memory locations. The cache window can be a subset of the entire circular buffer. If contents within the cache window are identified as persistent data, the locations corresponding to the persistent data can be identified as permanent memory locations. The position of the cache within the circular buffer can be frozen based on the permanent memory locations. A write mask can be used to maintain the contents of the permanent memory locations, while the remainder of the cache is configured as a temporary circular buffer. Operation of the cache returns to the entire circular buffer once the contents of the permanent memory locations no longer need to be maintained.

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Berkeley, CA, United States of America

Mark R Goudy