Cypress Semiconductor Corporation

Quantance, Inc.

At&e Corporation

Seiko Epson Corporation

Seiko Corporation

Radiocom Corporation

Mark R Gehring

Serge Francois Drogi

Vikas Vinayak

Nathan Y Moyal

Russell R Moen

Martin Tomasz

Lawrence H Ragan

Brent R Jensen

Eric P Mitchell

Joseph D Stenger

Richard R Suter

Lawrence Ragan

Cary Renzema

Jeremy Lubkin

David Gordon Wright

Daniel J Park

Gary A Price

An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.

RF power amplifier controller circuit including calibrated phase control loop

A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.

Phase error de-glitching circuit and method of operating

In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

Tri-stating a phase locked loop to conserve power

A method of communication between a first transceiver having a first local oscillator set at a first frequency and a second transceiver having a second local oscillator set at a second frequency disclosed. The method includes transmitting a first signal at a first frequency from the first transceiver to the second transceiver, transmitting a second signal at the second frequency from the second transceiver to the first transceiver, and receiving the second signal at the first transceiver. The method further includes maintaining the first local oscillator at the first frequency and the second local oscillator at the second frequency during the transmitting of the first signal, during the receiving of the first signal, during the transmitting of the second signal, and during the receiving of the second signal.

Circuit and method for selectable high/low side injection in an intermediate frequency transceiver

Wireless devices transmit and receive radio signals based upon reference frequencies generated by crystal oscillators. If the reference frequencies of the transmitter and the receiver are different, the radio signals may not be received properly or may not be received at all. A measurement circuit measures the amount of error or signal corruption in the radio signals due to the reference frequency offset between the transmitter and the receiver. A frequency offset circuit generates an offset operating frequency in the transmitter or the receiver to align or calibrate the operating frequencies of the devices.

Apparatus and method for frequency calibration between two radios

A logarithmic detector circuit including a drive circuit to receive a modulated input signal and generate a buffered modulated signal, a signal shaping circuit coupled to the drive circuit and configured to shape a voltage range of the buffered modulated signal to generate a shaped modulated signal, and a detecting circuit to detect the shaped modulated signal to generate an output signal substantially proportional to a logarithm of an amplitude of the modulated input signal.

Low noise logarithmic detector

A circuit including a subcircuit having differential signals, and a feedback circuit coupled to the subcircuit. The feedback circuit is configured to measure an offset between the differential signals, to generate a calibration signal in response to the measurement, and to reduce the offset in response to the calibration signal.

Apparatus and method for calibrating mixer offset

An improved Received Signal Strength Indicator (RSSI) circuit and method is provided herein for quickly and accurately detecting the strength of a received signal. The circuit described herein provides a more accurate RSSI signal, while consuming less power and die area, by utilizing digital rather than analog summing.

Digital received signal strength indicator (RSSI) circuit and method for detecting the strength of a received signal

Systems and method for tracking different types of transconductance cells is shown and described. In these multi-cell systems, the addition of one or more tracking control modules allows circuit designers to advantageously incorporate multiple transconductor topologies and their uniquely beneficial characteristics into their designs, without eradicating its centralized multi-cell tuning functionality.

Circuit for creating tracking transconductors of different types

A transmitter digital signal processor (DSP) circuit has a transmit frequency represented by n-bit data output from a look up table (LUT). The n-bit data is outputted to an n-bit accumulator structured to overflow at a rate based on the output n-bit data to output a phase. The circuit further has device structured to add an n-bit signed constant to the accumulator to offset the frequency represented by the n-bit data output from the LUT. A transceiver on a semiconductor chip may include as part of a transmitter circuit, a transmit DSP circuit that has the LUT, accumulator and device providing an n-bit signed constant to the accumulator to offset a transmit frequency in order to allow a receiver circuit on the transceiver to communicate directly with the transmitter circuit, and thus allowing testing of the transceiver.

Frequency offset and method of offsetting

A differential crystal oscillator electronic circuit. Embodiments of the present invention include circuits comprising two substantially similar oscillator circuits. The oscillator circuits may be coupled to a common crystal or ceramic resonator. Embodiments of the present invention are especially well suited to implementation within integrated circuits where their superior common mode and supply rejection function beneficially in opposition to the naturally high coupling characteristics of integrated circuits. Further, by naturally furnishing differential signals, these low noise signals may be used directly by other differential circuits on an integrated circuit, without requiring additional single ended to differential conversion circuitry.

Differential crystal oscillator

A method and system for initiating the oscillation of a crystal that controls a crystal oscillator by applying an initiating pulse to said crystal. The initiating pulse having a pulse width less than one half the periodicity of said crystal.

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Portland, OR, United States of America

Mark R Gehring