International Business Machines Corporation

Mark R Beckenbaugh

John William Zack

Michael D Cesky

Nicholas G Young

Eric John Lukes

Aj KleinOsowski

Jason J Freerkesn

Faye D Baker

Mark D Levy

Byron D Scott

Laura Marie Zumbrunnen

Jay A Lawrence

Lily L Wang

Jason J Freerksen

A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.

Variable performance ranking and modification in design for manufacturability of circuits

A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book.

Method for radiation tolerance by implant well notching

In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined. A cost is assigned to each placement, the cost indicating an amount of jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater jog would be created in the masking process than would be created by a placement assigned a lesser cost. A placement having a lowest cost of the plurality of possible placements is selected.

Auto-routing small jog eliminator

A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.

Method for radiation tolerance by logic book folding

A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a width difference between a width of the wire and a width of the source, and dividing the width difference by the width of the wire; and modifying a size of the wire if the first size differential is less than a maximum width percentage and if a length of the source is less than a length range specified by a user.

System and method for auto-routing jog elimination

A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a first width difference between a length of the wire and a width of the source, and dividing the first width difference by the width of the source; detecting a second size differential between the wire and the source if the first size differential is less than a maximum length percentage by calculating a second width difference between the width of the source and a width of the wire, and dividing the second width difference by the width of the source; and modifying a size of the wire if the second size differential is less than a maximum width percentage.

Growing community of inventors

Rochester, MN, United States of America

Mark R Beckenbaugh