Nxp B.v.

Nxp USA, Inc.

St-Ericsson Sa

Ampleon Netherlands B.v.

Samba Holdco Netherlands B.v.

Npx B.v.

Mark Pieter Van Der Heijden

Mustafa Acar

Jozef Reinerus Maria Bergervoet

Xin Yang

Jan Sophia Vromans

Gerben Willem De Jong

Melina Apostolidou

Gian Hoogzaad

Tony Vanhoucke

Jasper Pijl

Robert Bogdan Staszewski

Joseph Staudinger

Elie A Maalouf

Lukas Frederik Tiemeijer

Leonardus Cornelis Nicolaas De Vreede

Jawad Hussain Qureshi

Seyed Amir Reza Ahmadi Mehr

Ivan Mitkov Zahariev

Rik Jos

Amin Hamidian

Koen Buisman

Leo De Vreede

David Angel Calvillo Cortes

Leo C N De Vreede

Antonius Johannes Matheus De Graaw

Marco D'Avino

Ivan Matkov Zahariev

Bilal Elkassir

Michel Wilhelmus Arnoldus Groenewegen

Alessandro Baiano

David Calvillo Cortes

Leo CN De Vreede

An analog amplitude pre-distortion circuit includes a Radio Frequency, RF, input for receiving an RF signal. The circuit also includes an amplifier stage comprising an amplifier stage input for receiving the RF signal from the RF input, where the amplifier stage is operable to amplify the RF signal to produce an amplified RF signal. The circuit further includes a bias circuit. The bias circuit includes a detector stage for detecting an amplitude of the RF signal, and for producing a correction signal based on the amplitude of the RF signal. The bias circuit also includes a bias application stage coupled to the amplifier stage input.

Analog amplitude pre-distortion circuit and method

A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.

Multiple-stage Doherty power amplifiers implemented with multiple semiconductor technologies

A metal oxide semiconductor, MOS, device () is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias. A plurality of local interconnect layers, LIL, () are connected respectively to the least one source terminal and at least one drain terminal through the number of respective contact vias, wherein the at least one source terminal and the at least one drain terminal respectively connected to the plurality of LIL () are configured such that: the at least one source terminal and the at least one drain terminal do not overlap in a first direction () and a second direction () that is orthogonal to the first direction (); and the at least one source terminal and the at least one drain terminal do not overlap or only a proportion of the at least one source terminal and the at least one drain terminal overlap in a third direction (), where the third direction () is orthogonal to both the first direction () and the second direction ().

Metal oxide semiconductor device

A multiple-stage splitter/combiner circuit includes first and second splitter/combiner circuits coupled together. The first splitter/combiner circuit has first, second, and third input/output (I/O) ports, a first quarter wave line with a first end coupled to the first I/O port and a second end coupled to the second I/O port, a second quarter wave line with a first end coupled to the first I/O port and a second end coupled to the third I/O port, and a first resistor with first and second terminals coupled to the second and third I/O ports, respectively. The second splitter/combiner circuit has fourth, fifth, and sixth I/O ports, and a ring of multiple quarter wave lines, which includes third and fourth quarter wave lines. The third and fourth quarter wave lines each extend from the fourth I/O port in different directions from each other to the fifth and sixth I/O ports, respectively.

Beamformer integrated circuits with multiple-stage hybrid splitter/combiner circuits

A radio frequency, RF, auto-transformer circuit () and method () of constructing a RF auto-transformer are described. The RF, auto-transformer circuit () includes: an inner coil formed () with a first metal layer (MT) to create a first shunt inductor (), wherein at least a portion of the inner coil is overlayed () with a second metal layer (MT) that creates a first series inductor () that exhibits inductive coupling to the first shunt inductor (). An outer coil is formed () with the first metal layer (MT) that creates a second series inductor (), where the outer coil is located adjacent the inner coil and provides inductive coupling between the second series inductor () and each of the first shunt inductor () and first series inductor (). At least a portion of the outer coil is overlayed () with the second metal layer (MT) that creates a second shunt inductor () that exhibits inductive coupling between the second shunt inductor () and each of the first shunt inductor () and first series inductor () and second series inductor (). The outer coil is connected () to the inner coil using vias and the respective first metal layer (MT) is connected to the second layer (MT) using vias.

Radio frequency auto-transformer, radio frequency device and method of construction of an auto-transformer

A Wilkinson power combiner () is described that includes: at least one input port () coupled to at least one output port () by at least two power combining stages. A first power combining stage () of the at least two power combining stages is configured as a single-stage first frequency pass circuit and a second power combining stage () of the at least two stages is configured as a single-stage second frequency pass circuit, and wherein the first frequency is different to the second frequency.

Wilkinson power combiner, communication unit and method therefor

A Wilkinson power combiner () is described that includes a high-pass, HP, frequency circuit (), wherein the HP frequency circuit () comprises at least one of: (i) one input port () coupled to at least two output ports () via at least two paths; and an input shunt inductor () coupling the input port () to ground; wherein the one input port () is coupled to the at least two output ports () via respective series capacitances () on the at least two paths, which in cooperation with the input shunt inductor () forms a first HP frequency circuit; and (ii) at least one resistor ()-inductor (), R-L isolation circuit () configured to couple the at least two output ports () that forms a second HP frequency circuit.

An inductor and a method of making an inductor. The inductor includes a stack of dielectric layers. The inductor also includes a plurality of metal levels comprising patterned metallic features of the inductor. Each metal level is located at an interface between adjacent dielectric layers in the stack. The patterned metallic features include a first plurality of inductor windings arranged in a substantially flat spiral in one of the metal levels. The patterned metallic features also include a second plurality of inductor windings in which each winding is located in a respective one of the plurality of metal levels. The first plurality of windings is connected in series with the second plurality of windings.

Inductor and method of making an inductor

A radio frequency, RF, switch circuit () includes at least one first PiN diode device () configured to sink or source a first alternating current; and an impedance inversion circuit (), connected to the at least one first PiN diode device and arranged to provide a transformed impedance between a first side of the impedance inversion circuit and a second side of the impedance inversion circuit. The RF switch further includes a second diode-based device () configured to source or sink a second alternating current; and a bias circuit () connected to at least one of the at least one first PiN diode device and the second diode-based device, wherein the at least one first PiN diode device cooperates with the second diode-based device as a push-pull current circuit.

Radio frequency switch circuit, communication unit and method therefor

An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.

Radio-frequency amplifier

Switch arrangement

A power amplifier. The power amplifier includes a plurality of parallel coupled transistors. Each transistor has a control terminal coupled to receive a signal to be amplified and an output terminal coupled to a node. The power amplifier also includes a matching network having an input coupled to the node and an output coupleable to a load. The power amplifier further includes a first circuit branch forming a choke and harmonic trap of the power amplifier. The first circuit branch includes a first inductance, a second inductance and a first capacitor. The first inductance has a first terminal coupled to the node and a second terminal coupled to a first terminal of the second inductance. A second terminal of the second inductance is coupled to AC ground. The first capacitor is coupled in parallel with the second inductance.

Power amplifier

A bias circuit for a bipolar RF amplifier is described. The bias circuit includes a current source coupled to a bias network. The bias network supplies a base current to the transistors in the amplifier circuit of the bipolar RF amplifier. The bias circuit includes a buffer coupled to the bias network and to the bipolar RF amplifier. The buffer provides additional base current to the amplifier circuit of bipolar RF amplifier and sinks avalanche current generated by the amplifier circuit of the bipolar RF amplifier.

Bias circuit

An RF amplifier is described including an input, an output, a parallel arrangement of a first branch and at least one further branch, each branch comprising a bipolar transistor in a degenerative emitter configuration having a base coupled to the input, a collector coupled to a common collector node, and an emitter degeneration impedance arranged between the emitter and a common rail. The common collector node is coupled to the output, the base of the first branch bipolar transistor is biased at a first bias voltage and the base of the at least one further branch bipolar transistor is biased at a bias voltage offset from the first bias voltage. In operation of the RF amplifier a IM3 distortion current output by the first branch bipolar transistor is in antiphase to a IM3 distortion current output by the at least one further branch bipolar transistor.

RF amplifier

A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.

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Eindhoven, Netherlands

Mark Pieter Van Der Heijden