International Business Machines Corporation

Mark Peter Mendell

Yaoqing Gao

Roch Georges Archambault

Ronald Ian McIntosh

James Lawrence McInnes

Allan Russell Martin

Michael K Gschwind

Kun-Lung Wu

Alexandre E Eichenberger

John A Gunnels

Bugra Gedik

Raul Esteban Silvera

Henrique Andrade

Gheorghe Calin Cascaval

Robert F Enenkel

Robert William Hay

Graham K Yiu

Allen Russell Martin

Howard W Nasgaard

Graham Yiu

A code region of an application is instrumented by a multi-pass profiler with first annotations for generating profile data. The application is executed with the first annotations, wherein executing the application with the first annotations generates first profile data for the code region. The multi-pass profiler identifies, from the first profile data, the code region as a delinquent code region. The multi-pass profiler determines second annotations based, at least in part, on the first profile data and the at least one of the first annotations that defines the delinquent code region. The multi-pass profiler instruments, based on the first profile data, a code sub-region of the delinquent code region with the second annotations for generating profile data. The application is executed with second annotations, wherein executing the application with the second annotations generates second profile data for the code sub-region.

Multiple pass compiler instrumentation infrastructure

Systems, methods and computer products for cross-thread scheduling. Exemplary embodiments include a cross thread scheduling method for compiling code, the method including scheduling a scheduling unit with a scheduler sub-operation in response to the scheduling unit being in a non-multithreaded part of the code and scheduling the scheduling unit with a cross-thread scheduler sub-operation in response to the scheduling unit being in a multithreaded part of the code.

Systems, methods and computer products for cross-thread scheduling

A computer implemented method, software infrastructure and computer usable program code for improving application performance. A delinquent memory operation instruction is identified. A delinquent memory operation instruction is an instruction associated with cache misses that exceeds a threshold number of cache misses. A directive is inserted in a code region associated with the delinquent memory operation to form annotated code. The directive indicates an address of the delinquent memory operation instruction and a number of memory latency cycles expected to be required for the delinquent memory operation instruction to execute. The information included in the annotated code is used to optimize execution of an application associated with the delinquent memory operation instruction.

Uniform external and internal interfaces for delinquent memory operations to facilitate cache optimization

A method and computer program product for selecting an expression evaluation technique for domain-specific language (DSL) compilation. An application written in DSL for a programming task is provided, the application including a plurality of components configured by expressions. A technique that most quickly implements the programming task is selected from a plurality of techniques for evaluating the expressions. The DSL application is compiled in accordance with the selected expression evaluation technique to generate general-purpose programming language (GPL) code.

Method of selecting an expression evaluation technique for domain-specific language compilation

A method, apparatus, and computer instructions for processing instructions. A data dependency graph is built. The data dependency graph is analyzed for recurrences, and unpipelined instructions that lie outside of the recurrences are expanded.

Method and apparatus for determining the profitability of expanding unpipelined instructions

An apparatus and method for removing stores to local variables that are not aliased by other variables or to variables which have already been removed by previous optimizations prior to performing dead store elimination optimization are provided. With the method and apparatus, instructions that include a memory reference to a local variable that is not modified by other instructions are identified. For these instructions, an identifier of the variable referenced is maintained in a data structure along with the location of the store instruction in the procedure (for a store instruction) or a load indicator (for a load instruction). The data structure is then traversed to see if there are any store instructions referencing a variable that does not have a corresponding load instruction referencing the same variable. Such store instructions are eliminated prior to performing traditional dead store elimination.

Apparatus and method for linear dead store elimination

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Toronto, Canada

Mark Peter Mendell