International Rectifier Corporation

Infineon Technologies Americas Corp.

Infineon Technologies Ag

Mark Pavier

Andrew Neil Sawle

Daniel Cutler

Eung San Cho

Martin Standing

Daniel Marvin Kinzer

Ajit Dubhashi

Angela Kessler

Michael Sielaff

Wolfram Hable

Christoph Glacer

Ulrich Krumbein

David Tumpold

Tim Sammon

Sven Fuchs

Norman Glyn Connah

Clive O'Dell

Adam I Amali

Jorge Cerezo

Charles Rimbert-Riviere

Anton Pugatschow

Glyn Connah

Rupert Burbidge

Andy Farlow

Marco Sobkowiak

Rachel Anderson

Scott Palmer

Bruno Charles Nadd

Bernd Goller

Dominic Maier

David Paul Jones

Chee Yang Ng

Marco Soldano

Josef Maerz

Thai Kee Gan

David C Tam

Hazel Deborah Schofield

Ke Yan Tean

Robert J Clarke

Paul Christopher Westmarland

Frank Püschner

Martin Carroll

Stephen Oliver

Azlina Kassim

Ritu Sodhi

Susan Johns

Stuart Cardwell

Mohd Hasrul Zulkifli

George Pearson

Danish Khatri

Vijay Bolloju

Leigh Cormie

Tobias Mittereder

David Bushnell

Phillip Adamson

Kenneth McCartney

Chris Davis

Joachim Eder

Siyuan Qi

Bernd Ebersberger

Clive O'dell

Hugh Richard

A wafer-level package sensor device including a capacitive sensor, a controller which is electrically conductively connected to the sensor, wherein the capacitive sensor is formed by partially overlapping redistribution layer tracks of the wafer-level package sensor device formed in different planes, and multiple contact surfaces connected to the controller, which are configured to electrically couple to a chip card module carrier using a flip-chip connection.

Wafer-level package sensor device

A semiconductor device includes a first carrier, a first external contact, a second external contact, and a first semiconductor die. The first semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The first semiconductor die is disposed with the first main face on the first carrier. A clip connects the second contact pad and the second external contact. A first wire is connected with the first external contact. The first wire is disposed at least partially under the clip.

Semiconductor die being connected with a clip and a wire which is partially disposed under the clip

A sound transducer device includes a multilayer component board having a first side and an opposite second side, and a sound port extending between the first and second sides of the multilayer component board. The sound transducer also includes a MEMS sound transducer die including a suspended membrane structure, wherein the MEMS sound transducer die is arranged at the first side of the multilayer component board such that the suspended membrane structure is in fluid communication with the sound port. The sound transducer also includes a mesh structure for providing an environmental barrier, the mesh structure covering the sound port from either one of the first and second sides of the multilayer component board.

Methods of environmental protection for silicon MEMS structures in cavity packages

An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.

Three level interconnect clip

The present disclosure concerns an emitter package for a photoacoustic sensor, the emitter package comprising a MEMS infrared radiation source for emitting pulsed infrared radiation in a first wavelength range. The MEMS infrared radiation source may be arranged on a substrate. The emitter package may further comprise a rigid wall structure being arranged on the substrate and laterally surrounding a periphery of the MEMS infrared radiation source. The emitter package may further comprise a lid structure being attached to the rigid wall structure, the lid structure comprising a filter structure for filtering the infrared radiation emitted from the MEMS infrared radiation source and for providing a filtered infrared radiation in a reduced second wavelength range.

Emitter package for a photoacoustic sensor

A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.

Semiconductor assembly with conductive frame for I/O standoff and thermal dissipation

A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.

Molded package with chip carrier comprising brazed electrically conductive layers

A method includes coupling a first major surface of a semiconductor die to a metallic body, depositing an insulation body over said semiconductor die, and removing a portion of said insulation body to expose a plurality of electrodes of said semiconductor die on a second major surface of said semiconductor die opposite said first surface. The method further includes forming a plurality of conductive pads over the plurality of electrodes, each conductive pad of said plurality of conductive pads providing an external connection for a respective one of said plurality of electrodes, wherein each conductive pad of said plurality of conductive pads has an area larger than an area of said respective one of said plurality of electrodes to which the respective conforming conductive pad of said plurality of conductive pads is coupled and extending over said insulation body.

Semiconductor package including a semiconductor die having redistributed pads

A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

Method for fabricating a semiconductor package with conductive carrier integrated heat spreader

A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.

In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.

Semiconductor package including conductive carrier coupled power switches

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.

Power semiconductor package having vertically stacked driver IC

In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.

Power converter package including top-drain configured power FET

According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.

Surface mountable power components

Growing community of inventors

Felbridge, United Kingdom

Mark Pavier