Xilinx, Inc.

Mark Paluszkiewicz

Ralph D Wittig

Henry E Styles

Richard S Ballantyne

Paul R Schumacher

Robert D Turney

Prasanna Sundararajan

Kornelis Antonius Vissers

Brandon Blodget

Catalin Baetoniu

Approaches for communicating data from a source device to a target device. In one approach, a communicated data value is segmented into a plurality of data chunks at the source device. A sequence of interrupt transactions is transmitted from the source device to a system bus. The transmitting of each interrupt transaction in the sequence includes transmitting a target identifier on an address bus of the system bus, and the target identifier of each interrupt transaction in the sequence includes a respective one of the data chunks. The sequence of interrupt transactions from the system bus is received at the target device. The communicated data value is reassembled at the target device from the data chunks in the target identifier of the interrupt transactions in the sequence.

Segmentation and reassembly of a data value communicated via interrupt transactions

Within a system comprising a programmable integrated circuit (IC), a method can include storing a first configuration within the system in a read-only memory that is independent of the programmable IC. The programmable IC, being loaded with the first configuration, comprises a circuit that accesses a data source external to the system over a communication link. A second configuration can be downloaded by the programmable IC from the data source. The second configuration can be stored within a random access memory within the system that is independent of the programmable IC. Responsive to a reconfiguration event, the programmable IC can be loaded with the second configuration from the random access memory.

Providing multiple selectable configuration sources for programmable integrated circuits with fail safe mechanism

In one embodiment, an output driver is disclosed. The output driver has a first driving device (Q) that has a first terminal coupled to a bus line terminal, and a second driving device (Q) that has a first terminal coupled to the bus line terminal. The first driving device (Q) is configured to couple the bus line terminal to a reference voltage when activated by a first control signal, and the second driving device (Q) is configured to couple the bus line terminal to a first supply voltage (Vcc) when the second driving device (Q) is activated by a second control signal. The output driver also has a controller configured to activate the second control signal after the first control signal is deactivated. The second control signal remains active for a first fixed period of time.

System and method for open drain/open collector structures in an integrated circuit

Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.

Generic buffer circuits and methods for out of band signaling

Method and apparatus for implementing first-in-first-out (FIFO) memories using time-multiplexed memory in an integrated circuit are described. A block random access memory (BRAM) circuit embedded in the integrated circuit is provided. The BRAM includes at least one port responsive to a respective at least one BRAM clock signal. FIFO logic is configured to implement a plurality of FIFOs in the BRAM having a plurality of interfaces. Multiplexer logic is configured to selectively couple the plurality of output interfaces of the FIFO logic to the at least one port of the BRAM circuit responsive to at least one FIFO clock signal. Each of the at least one BRAM clock signal has at least twice the frequency of a respective one of the at least one FIFO clock signal.

Method and apparatus for implementing FIFOs using time-multiplexed memory in an integrated circuit

Various approaches for embedding identifier information in a configuration bitstream for a programmable logic device (PLD) are disclosed. In various embodiments, the bits in the configuration bitstream that are unused in implementing a the design are identified. The identifier information is encrypted, and a subset of the unused bits are selected using a pseudo-random function. The encrypted identifier information is placed in the selected subset of unused bits. Decryption is accomplished by reversing the encryption approach.

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Schaumburg, IL, United States of America

Mark Paluszkiewicz