Micron Technology Incorporated

Intel Corporation

Mark P Leinwander

Sean Stephen Eilert

Jared E Hulbert

Stephen Bowers

Samuel David Post

Gurkirat Billing

Steven E Wells

Robert N Hasbun

Jeffrey L McVay

Joseph Edgington

Sam Post

An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass configuration routing information and initiate instructions to disperse portions of the database to neighboring die using an interface that handles inter-die communication. Information is then extracted from the pool of autonomous memory and passed through a host interface to the host controller.

Autonomous memory architecture

An embodiment of a semiconductor apparatus may include technology to provide information related to one or more parity capabilities of a controller and a persistent storage media in response to an inquiry from a host device, and adjust one or more parameters related to the one or more parity capabilities of the controller and the persistent storage media in response to a request from the host device. Other embodiments are disclosed and claimed.

XOR parity management on a physically addressable solid state drive

In various embodiments, a hierarchical memory device having multiple interfaces with different memory formats and may include a Phase Change Memory (PCM) device. An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy and/or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. Other embodiments are discussed.

Memory device for a hierarchical memory architecture

Memory devices connected in a chain topology to a host controller that communicate using Low Voltage Differential Signaling (LVDS) and out-of-band signaling.

Using out-of-band signaling to communicate with daisy chained nonvolatile memories

In various embodiments, a hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy and/or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. Other embodiments are discussed.

An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance.

Autonomous memory subsystem architecture

Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.

Switchable on-die memory error correcting engine

A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.

Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus (e.g., block-based storage device) includes a storage array to store data and a memory-mapped interface that is coupled to the storage array. The memory-mapped interface includes memory-mapped memory space. The memory-mapped interface receives direct access requests from a host to directly access memory-mapped files. The apparatus also includes a block interface that is coupled to the storage array. The block interface receives block requests from a storage driver to access the storage array.

Growing community of inventors

Folsom, CA, United States of America

Mark P Leinwander