Broadcom Corporation

Intel Corporation

Marvell International Limited

Marvellworld Trade Ltd.

Other

Micron Technology Incorporated

Nxp B.v.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Marvell Israel (misl) Ltd.

Calxeda, Inc.

Barvell World Trade Ltd.

Mark Norman Fullerton

Moinul H Khan

Anitha Kona

Paul Penzes

Dennis M O'Connor

Love Kothari

Veronica Alarcon

Lawrence John Madar, Iii

Walid Nabhane

Bhupesh Kharwa

Ray Richardson

Ofer Bar-Shalom

John P Brizek

David Wheeler

Sam H Liu

Amit Dor

Alon Tsafrir

Chih-Tsung Hsieh

Hao-zheng Lee

John S Walley

Claude G Hayek

Nigel C Paver

Vasudev Bibikar

Peter D Mueller

Lance Flake

Nir Paz

Charles Roth

Vinay Bhasin

Chaoyang Zhao

Joyjit Nath

Arthur Miller

Robert Morris

Ronak Subhas Patel

Nir Nossenson

Sehat Sutardja

Sujat Jamil

Hang T Nguyen

Steven J Tu

R Frank O'Bleness

Bradley C Aldrich

David E Miner

Samantha J Edirisooriya

Hong-Yi Chen

Lawrence Loren Case

Premanand Sakarda

Jay S Heeb

Stephen J Strazdus

Nancy G Woodbridge

Mukesh Patel

Sathish Kumar Radhakrishnan

Murli Ganeshan

Tim Sippel

Hwisung Jung

Wing K Yu

Ajat Hukkoo

Rajith Kumar Mavila

Barry Ross Evans

Rupal Parikh

William T Maghielse

Jianwei Liu

Anthony Jebson

Deli Deng

Jeffrey Scott Boyer

Loic Leconte

Brent Mulholland

Ajmal A Godil

Liang Deng

Zhongmin Zhang

Sebastian Stappert

Kailesh B Bavaria

Rajesh Rajan

Mathieu Blazy-Winning

Ravi S Setty

Greg Goodemote

Thomas Ernst Friedrich Wille

Khan Kibria

Niray P Dagli

Sathis K Radhakrishnan

Jay Heeb

A system-on-chip (SoC) method and apparatus are disclosed for checking end-to-end integrity of communications over an network interconnect, where the SoC includes an initiator subsystem connected over the network interconnect to a target subsystem, wherein a first integrity module is configured to compute a first integrity value based on regular transaction messages sent or received by the initiator subsystem and to send a protecting information transaction (PIT) message over the network interconnect to the target subsystem, wherein a second integrity module is configured to compute a second integrity value based on regular transaction messages sent or received by the destination subsystem and to send a PIT response message over the network interconnect to the initiator subsystem, and wherein a compatibility module compares the first and second integrity values to verify the end-to-end integrity of the regular transaction messages sent or received over the network interconnect.

End-to-end transaction integrity through standard interconnect

A data processing system includes a plurality of subsystems, a plurality of local security controllers, and a central security controller. Each subsystem of the plurality of subsystems has a security component for providing a security function. A local security controller corresponds to each one of the subsystems. Each local security controller ensures compliance of the security component with local security policies of the subsystem to which the local security controller corresponds. The central security controller is coupled to the local security controller of each of the plurality of subsystems. The central security controller ensures data processing system compliance with system wide security policies. In the event of a detected security violation, the local security controller may respond automatically, without involvement of the central security controller. A method for securing the data processing system is also provided.

Data processing system having distributed security controller with local control and method for securing the data processing system

Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.

Adaptive clocking scheme

Controlling a power supply which supplies a voltage to target circuit of an integrated circuit. An adjustable delay line powered by the supply voltage is co-located on the IC with the target circuit. The adjustable delay line is subjected to substantially the same operating conditions as the target circuit. A control unit measures a delay time of the adjustable delay line. Based on the measured delay time, the control unit outputs a control signal by which the power supply adjusts the supply voltage. The adjustable delay line comprises multiple distinct delay elements, each with delay properties and responsivity to changes in operating conditions. Each delay element emulates delay properties of physical elements (e.g., gates and wires) in the target circuit. In this manner, power consumption may be reduced, while still maintaining proper operation of the target circuit.

Closed loop voltage control using adjustable delay lines

Aspects of enhanced recovery mechanisms are described. A predetermined operating parameter for a power rail is set at the outset of system start. Afterwards, a processor is released to start with a power management circuit. In turn, the power management circuit receives a default operating parameter for the power rail from the processor, and stores the default operating parameter. The power management circuit also receives a runtime operating parameter for the power rail from the processor and modifies the operating parameter for the power rail according to the runtime operating parameter. If an error condition in the processor is encountered, the power management circuit may modify the operating parameter for the power rail according to the default operating parameter in response to a reset control signal from the processor. Use of the default operating parameter for the power rail may assist the processor to recover from the error condition.

Enhanced recovery mechanisms

A method for serial interface clock domain crossing includes identifying a data communication command received over a serial interface. An address is decoded to determine whether the address falls within a direct latch address range of a register bank. Data is communicated over the serial interface. A multiplexed output clock is generated, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.

Clock domain crossing serial interface

Aspects of power mode register reduction and power rail bring up enhancements are described. In one embodiment, an operating parameter for a first power rail is set by power management circuit according to a predetermined programmed setting. In connection with a wait time, the power rail is enabled, and a processor is released to start. In turn, at least one of a command to modify the operating parameter for the first power rail or a command to set an operating parameter for a second power rail is received from the processor over a high speed interface. By accessing a grouped operating register for a group of power rails, the processor can update or modify settings of an entire group of power rails at one time. In connection with the processor, the power management circuit can power up a plurality of power rails in a flexible and efficient manner.

Power mode register reduction and power rail bring up enhancement

Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.

Systems and methods for distributing an aging burden among processor cores

Adaptive clocking scheme to accommodate supply voltage transients

A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.

Secure controller for block oriented storage

An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.

Electronics device capable of efficient communication between components with asyncronous clocks

Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by 'pre-heating' the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.

Pre-heating for reduced subthreshold leakage

A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

Dynamic core switching

In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.

Method and apparatus for a trust processor

Growing community of inventors

Austin, TX, United States of America

Mark Norman Fullerton