American Microsystems, Inc.

Ami Semiconductor, Inc.

Waferscale Integration, Inc.

Semiconductor Components Industries, LLC

Mark Michael Nelson

Rustom F Irani

Subhash Madhukar Deshmukh

Boaz Eitan

Thierry Coffi Herve Yao

Reza Kazerounian

Gregory James Scott

John J Naughton

Larry Willis Petersen

Brett N Williams

Jagdish Prasad

An electronic device includes a first memory cell and a second memory cell, of a nonvolatile memory array. The first memory cell includes a body region, a gate structure, a source region, and a drain region. The second memory cell includes a body region, a gate structure, a source region, and a drain region. In one embodiment, the body of the second memory cell is physically isolated from the body region of the first memory cell. A bitline segment is electrically connected to the drain region of the first memory cell and to the drain region of the second memory cell.

Device including memory array and method thereof

A method for forming a pre-metallization layer on an underlying micro-structure, and a corresponding micro-structure formed by the method. The micro-structure may be a semiconductor circuit and/or a Micro-Electro-Mechanical Systems (MEMS) device. A first layer of undoped silicate glass is deposited on a micro-structure. Then, a layer of phospho silicate glass is deposited on the first layer of undoped silicate glass. This combination is then densified by applying a temperature to the combination that is sufficient to densify the layer of phospho-silicate glass, while being below the glass flow temperature. After densification, a second layer of undoped silicate glass is deposited on the densified layer of phospho silicate glass. Finally, the upper surface of the second layer of undoped silicate glass is polished using a chemical mechanical polishing process. The result is a dielectric layer of high density and low stress, and that reduces soft errors and defects.

Methods for manufacturing a soft error and defect resistant pre-metal dielectric layer

Methods for protecting the sidewall of a metal interconnect component using Physical Vapor Deposition (PVD) processes and using a single barrier metal material. After forming the metal interconnect component, a single barrier metal is deposited on its sidewall using PVD. A subsequent anisotropic etching of the barrier metal removes the barrier metal from the horizontal surface except for some that still remains on the top surface of the metal interconnect layer. A dielectric layer is then formed over the metal interconnect component and the barrier metal. The unlanded via is etched through the dielectric layer to the metal interconnect component, and then filled with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers.

Methods for sidewall protection of metal interconnect for unlanded vias using physical vapor deposition

A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduced capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.

Use of irregularly shaped conductive filler features to improve planarization of the conductive layer while reducing parasitic capacitance introduced by the filler features

Characterization of plasma-induced damage in semiconductor manufacturing has long been considered unimportant because the damage had no discernable effect on circuit performance. With increasing transistor counts on an integrated circuit, the damage-induced parasitics are becoming increasingly important. Electrical characterization of such effects provides a far more sensitive method for determining the extent of damage and the effectiveness of efforts to repair the damage. A measurement of diode leakage current through a plasma-etch effect test diode which is formed completely within an active device region, removed from field oxide regions quantifies the extent of damage created by a plasma and the effectiveness of a repair technique that may be applied to the process.

Electrical diagnostic technique for silicon plasma-etch induced damage characterization

Characterization of plasma-induced damage in semiconductor manufacturing has long been considered unimportant because the damage had no discernible effect on circuit performance. With increasing transistor counts on an integrated circuit, the damage-induced parasitics are becoming increasingly important. Electrical characterization of such effects provides a far more sensitive method for determining the extent of damage and the effectiveness of efforts to repair the damage. A measurement of diode leakage current through a plasma-etch effect test diode which is formed completely within an active device region, removed from field oxide regions quantifies the extent of damage created by a plasma and the effectiveness of a repair technique that may be applied to the process.

Method for detecting and characterizing plasma-etch induced damage in an integrated circuit

A read only memory (ROM) array is disclosed which includes a) a voltage supply providing an operating voltage level, b) a plurality of word-lines, c) a multiplicity of ROM transistors, and d) a word-line clamper. The ROM transistors are divided into turned on and turned off transistors. Each ROM transistor has a gate connected to one of the word-lines, a gate oxide beneath the gate, whose thickness is less than 250 .ANG., and a channel beneath the gate oxide. The turned off transistors additionally have a ROM implant in their channel whose dosage is no larger than the amount which generates a predetermined desired minimal band-to-band tunneling current The ROM implant and gate oxide thickness define a threshold voltage for the tamed off tranistors, the threshold voltage being less than the operating voltage level. The word-line damper provides a word-line voltage to each of the word-lines, the word-line voltage being clamped to a voltage level no higher than the threshold voltage of the turned off transistor.

Operating method for ROM array which minimizes band-to-band tunneling

A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) etching the ROM oxide layer only from the periphery area as per a later-removed core protect mask, d) providing a gate oxide layer over the entirety of the ROM array, e) laying down polysilicon rows in the core area as per a polysilicon mask and f) implanting a ROM implant into selected areas of the core area, thereby to produce turned off core transistors. The thickness of the gate oxide layer and the ROM oxide layer are independent of each other.

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Pocatello, ID, United States of America

Mark Michael Nelson