Dialog Semiconductor (uk) Limited

Renesas Design (uk) Limited

Mark Mercer

Aravind Mangudi

Karthik Jayaraman

Kevin Dowdy

Holger Petersen

James C Steele

Bryan Quinones

Michael Jayo

John William Kesterson

Kevin Yi Cheng Chang

Chanchal Gupta

Kevin Chang

Pietro Gambetta

Kelly Consoer

Hyungtaek Chang

Jeffrey Kanner

Taek Chang

Bill McKillop

William McKillop

Muhammad Nabeel Rahman

A method of managing power and a power management circuit are presented. The power management circuit includes a three terminals switching converter coupled to a controller. The switching converter has a single inductor and two sets of switches. The first set of switches is coupled to an input terminal. The second set of switches is coupled to a battery terminal. The single inductor is provided between a first switching node and a second switching node. A controller is configured to generate a first error signal, and a second error signal and to provide the inductor current to the second terminal when the second error signal is greater than the first error signal or to the third terminal when the second error signal is less than the first error signal.

Power management circuit

The present document describes an error amplification circuit for a voltage regulator. The error amplification circuit comprises a differential error amplifier having a first input for a feedback signal of the voltage regulator and having a second input for a reference signal, wherein the differential error amplifier is configured to provide an amplifier output current in dependence of the signals at the first input and at the second input. Furthermore the error amplification circuit comprises a current sensing unit configured to sense the amplifier output current to provide a sensed current, a processing unit configured to process the sensed current to provide a processed current, and an adjustment resistor which is arranged in series with the second input of the differential error amplifier and to which the processed current is applied.

Broadband amplifier with DC gain error correction

The present document describes a power converter configured to convert electrical power at an input voltage at an input of the power converter to electrical power at an output voltage at an output of the power converter. The power converter comprises a first flying capacitor, a second flying capacitor and a third flying capacitor, as well as an inductor and a set of power switches. Furthermore, the power converter comprises a control unit configured to control the set of power switches such that during an operation cycle the power converter is operated in a first state and in a second state in a mutually exclusive manner.

Multipath hybrid regulator

The present document describes a power converter configured to convert electrical power at an input voltage at an input of the power converter to electrical power at an output voltage at an output of the power converter. The power converter comprises a first upper capacitor and a first lower capacitor, which are coupled with one another via a first mid node; a second upper capacitor and a second lower capacitor, which are coupled with one another via a second mid node; an inductor; and a set of power switches. In addition, the power converter comprises a control unit which is configured to control the set of power switches such that during an operation cycle the power converter is operated in a first main state and in a second main state in a mutually exclusive manner.

Dual path split-capacitor power converter

A multi-level power converter and a method using first, second, third and fourth switching elements, an inductor, and a flying capacitor are presented. A first terminal of the inductor may be connected to a switching terminal connecting the second and third switching elements. A first terminal of the flying capacitor may be connected to a terminal connecting the first and second elements. A second terminal of the flying capacitor may be connected to a terminal connecting the third and fourth switching elements. The multi-level power converter may have a first feedback circuit to generate control signals for setting the switching elements in a plurality of switching states for regulating an output voltage or an output current. The converter may have a second feedback circuit to generate control signals to allow the flying capacitor to be charged or discharged using an inductor current flowing through the inductor.

Multi-level power converter with light load flying capacitor voltage regulation

A method of managing power and a power management circuit operable in a plurality of modes are presented. The power management circuit includes a three terminals switching converter coupled to a controller. The switching converter has a single inductor, two sets of switches, a bypass switch and a transition switch. The first set of switches is coupled to an input terminal. The second set of switches is coupled to a battery terminal. The bypass switch is coupled between the battery terminal and a load terminal. The single inductor is provided between a first switching node and a second switching node. The transition switch is provided between the first switching node and the battery or the load terminal. A controller is configured to select a mode of operation by changing a state of at least one of the bypass switch and the transition switch.

The present document relates to power converters with multiple feedback loops. The present document relates to a power converter with at least two feedback loops. The power converter may comprise a first error amplifier and a first capacitive element. The power converter may comprise a second error amplifier and a second capacitive element, wherein the second error amplifier is configured to generate, based on a second reference value and a second feedback signal, a second error current for charging the second capacitive element. The power converter may comprise a selector circuit configured to generate a selection signal by comparing a first voltage of the first capacitive element and a second voltage of the second capacitive element. The power converter may comprise a first track amplifier circuit configured to establish an additional current path from a supply rail to the first capacitive element for accelerated charging of said first capacitive element.

Preventing inter-loop interference in a multi-feedback loop system

The present document relates to power converters with multiple feedback loops. The present document relates to a power converter with at least two feedback loops. The power converter may include a first error amplifier configured to generate a first error signal based on a first reference signal and a first feedback signal. The power converter may include a second error amplifier configured to generate a second error signal based on a second reference signal and a second feedback signal. The power converter may include a selector circuit configured to generate a selection signal by selecting the first error signal or the second error signal. The power converter may include a first clamp circuit configured to limit the first error signal to a first threshold value. The power converter may include a first threshold value generator circuit configured to generate the first threshold value dependent on the first error signal.

Adaptive error amplifier clamping in a multi-feedback loop system

Circuits and methods to enable wireless power transmission and reception are presented. A two-stage power converter has a boost regulator to boost an input voltage to an intermediate voltage. Moreover, the two-stage power converter may also comprise a charge pump coupled to the boost regulator to generate an output voltage based on the intermediated voltage. More particularly, the charge pump may comprise a plurality of transistor devices and a flying capacitor and the charge pump may be bypassed during a bypass mode of operation. Finally, the two-stage power converter may have control circuitry coupled to the charge pump. In particular, the control circuitry may generate a control voltage of a first transistor device of the plurality of transistor devices in order to regulate a discharge rate of the flying capacitor, during a transition phase from the bypass mode of operation to a normal mode of operation.

Charge pump transient response optimization by controlled flying capacitor discharge during bypass to switching mode transition

A regulation loop circuit and a method for a buck converter for receiving an input voltage and providing an output voltage are presented. The buck converter has a capacitive divider coupled to the input terminal and comprising a first capacitor, a second capacitor, and a plurality of switches. An inductor is coupled to the capacitive divider at a switching node and is coupled to the output terminal. The regulation loop circuit is coupled to the output terminal and a reference voltage. The loop regulates the output voltage based on the reference voltage by i) regulating a switching node voltage by switching the buck converter through a plurality of phases. and ii) maintaining an approximately equal duration for each phase.

Regulation loop circuit

A multi-level buck converter is provided with seamless transitions back and forth from synchronous to asynchronous low dropout modes of operation.

Asynchronous dropout transition for multi-level and single-level buck converters

A two-stage power converter includes a dual-level driver to control a current conducted by a switch transistor in a charge pump to control the charging of a flying capacitor in the charge pump.

Transient response optimization for charge-pump-based two-stage power converter

A multi-level buck converter is provided with multiple control loops to regulate the output voltage in the presence of over-current conditions and in the vicinity of a 50% duty cycle.

Multi-level buck converter with current limit and 50% duty cycle control

A gate drive circuit arranged to receive an input signal and provide an output signal to drive a gate of a transistor is presented. The gate drive circuit comprises a filter circuit arranged to attenuate a frequency band from the input signal when deriving the output signal from the input signal. The filter circuit contains programmable resistive elements, comprising: a first programmable resistive element arranged to adjust a low frequency gain and bandwidth of the gate drive circuit; a second programmable resistive element arranged to adjust a high frequency gain of the gate drive circuit; and a pair of programmable resistive elements arranged to adjust a driving gain of the gate drive circuit. A method of receiving an input signal and deriving an output signal from an input signal is also presented. The step of deriving an output signal comprises attenuating a frequency band from the input signal.

Gate driver

Driver circuits with S-shaped gate drive voltage curves for ramp-up and ramp-down of power field effect transistors are presented. In ramp-up, the S-shaped curve rapidly ramps the gate voltage of the power FET to its threshold. This ramp-up is self-terminating. The gate voltage of the power FET is slewed through saturation with a time constant. After a predetermined time, the gate of the power FET is driven to approach the supply voltage level. In ramp-down, the S-shaped curve rapidly ramps the gate voltage of the power FET down to its threshold voltage. This ramp-down is self-terminating. The gate voltage of the power FET is slewed through saturation. The gate-source voltage of the power FET is rapidly ramped down to zero. Such S-shaped curves for the gate drive signal allow the control of the transition times of the gate drive signal to acceptable levels of voltage/current spikes and electromagnetic interference.

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Phoenix, AZ, United States of America

Mark Mercer