Xilinx, Inc.

Mark Men Bon Ng

Shankar Lakkapragada

Scott Te-Sheng Lien

Jesse H Jenkins, Iv

Jose M Marquez

Tetse Jang

Iv Jesse H Jenkins

A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal. A circuit for minimizing power consumption in a device is also disclosed.

Circuit for and method of minimizing power consumption in an integrated circuit device

A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock signal adaptation occurs through duty cycle correction (DCC) to substantially achieve a 50% duty cycle. In an alternate embodiment, clock signal adaptation occurs through a multiplication operation that is applied to the clock signal to be adapted, whereby the multiplication operation is parameterizable to allow odd/even multiplication. In an alternate embodiment, clock signal adaptation occurs through a phase-shift operation that is applied to the clock signal to be adapted, whereby the phase-shift operation is parameterizable to allow all possible fractions and percentages of phase shifts.

Method and apparatus for counter-based clock signal adaptation

A method of employing memory cells of an integrated circuit is disclosed. The method comprises steps of storing configuration data in a plurality of memory cells of a memory of the integrated circuit; selecting unused memory cells of the memory of the integrated circuit for use as a scratchpad memory; providing access to the unused memory cells of the integrated circuit; and enabling use of the unused memory cell of the integrated circuit in a user mode as scratchpad memory. According to one embodiment of the invention, a plurality of input/output ports of the integrated circuit is coupled to a plurality of JTAG inputs coupled to the plurality of unused memory cells. A programmable logic device having memory cells for storing data, and a circuit employing a programmable logic device, are also disclosed.

Employing unused configuration memory cells as scratchpad memory

Circuit and method for employing unused configuration memory cells as scratchpad memory

Voltage level translation for open-drain circuitry is described. A logic isolation circuit includes a first buffer circuit configured for being switched between a first voltage transferable state and a first voltage non-transferable state. A first latch circuit is configured for being switched between a first reset state and a first non-reset state, the first reset state for setting the first latch circuit to a first reset condition. A second buffer circuit and second latch circuit are configured like the first buffer circuit and the first latch circuit. First and second input/output nodes are coupled to receive first and second logic level voltages, respectively. The first logic level voltage and the second logic level voltage are both for a same logic state, but the second logic level voltage is significantly greater than the first logic level voltage.

Growing community of inventors

Milpitas, CA, United States of America

Mark Men Bon Ng