University of Florida Research Foundation Inc

University of Connecticut

Technische Universitaet Berlin

Mark M Tehranipoor

Domenic J Forte

Haoting Shen

Navid Asadi-Zanjani

Navid Asadizanjani

Farimah Farahmandi

Adib Nahiyan

Shahin Tajik

Damon Woodard

Nathan Jessurun

Nidish Vashistha

Mir Tanjidur Rahman

Kun Yang

Fahim Rahman

Olivia Pauline Paradis

Bicky Shakya

Andrew C Stern

Qihang Shi

Huanyu Wang

Swarup Bhunia

Ronald Wilson

Fatemeh Ganji

Mukhil Azhagan Mallaiyan Sathiaseelan

Ulbert Botero

Jungmin Park

Mohammad Sazadur Rahman

Nitin Varshney

Ujjwal Guin

Jean-Pierre Seifert

Jacob C Harrison

Hangwei Lu

Various embodiments provide computer vision techniques for ensuring system- and component-level integrity via component characterization. Various embodiments may comprise computer vision systems that are configured to extract pin information from surface-mount device ('SMD') contours. Accordingly, the disclosed embodiments may include a computer vision system configured to detect the extremities of each pin in a SMD contour image based on a combination of at least one of machine learning and one or more PCB image collection datasets.

System and method for computer inspection of surface-mount devices

Methods and systems are directed to protect a target logic circuit against optical probing attacks and conceal a logic state in the target logic circuit. The method comprises designing a concealing logic circuit. The concealing logic circuit can be coupled to complement of input signals of the target logic circuit, inserted as neighbor logic circuit of the target logic circuit, and placed in close optical proximity to the target logic circuit. The concealing logic circuit can operate in the opposite operation mode or logic state of the target logic circuit in response to the complement of the input signals to the target logic circuit. The method can further comprise designing an evaluation circuit that generates the complement of the input signals and minimizes a path delay between the target logic circuit input and the concealing logic circuit input.

Apparatus for protecting against optical probing attacks

Various embodiments provide methods, systems, computer program products, apparatuses, and/or the like for assessing vulnerability of an IC design to fault injection attacks, such as through a security property-driven vulnerability assessment framework for efficiently evaluating faults with respect to certain security properties associated with the IC design. In one embodiment, a method is provided. The method includes generating, using a fault-injection technique specification, one or more fault models describing attributes of one or more faults. The method further includes selecting, using the fault models and executable security properties associated with a design file of an IC design, a fault list identifying a plurality of possible faults for the IC design. The method further includes identifying, based at least in part on performing a fault simulation on the design file with the fault list, critical locations of the IC design. The method further includes implementing protections at the critical locations.

Security property-driven vulnerability assessments of ICs against fault-injection attacks

A method includes in part, generating an electro-optical frequency map (EOFM) of an active layer of an integrated circuit (IC), retrieving a reference map of the IC, comparing the EOFM of the IC with the reference map to determine whether there is a match between an intensity of an identified region in the EOFM map and an intensity of a corresponding region of the reference map, and detecting one or more hardware trojans in the IC if there is no match. The reference map may be associated with a layout of an IC known not to include hardware trojans. The reference map also may be a second EOFM associated with the IC. Alternatively, the reference map may be generated by applying power to the IC, and applying a clock signal to the IC.

Systems and methods for laser probing for hardware trojan detection

Embodiments of the present disclosure provide methods, apparatus, systems, and computer program products for using an image of an integrated circuit (IC) including a plurality of cells to locate one or more target cells within the IC. Accordingly, in various embodiments, a footprint for each cell of the plurality of cells is encoded to transform the image of the IC into a two-dimensional string matrix. A string search algorithm is then applied on each encoded dopant region found in the two-dimensional string matrix using an encoded target layout cell to identify one or more candidate regions of interest within the image. Finally, a mask window is slid over each candidate region of interest while performing matching using match criteria to identify any target cells in the one or more target cells that are located within the candidate region of interest.

Knowledge-based object localization in images for hardware assurance

Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.

Hardness amplification of physical unclonable functions (PUFS)

Methods, apparatus and computer program product for protecting a confidential integrated circuit design process. The computer-implemented method includes receiving a design specification dataset from a first untrusted computing device; extracting confidential design specification data from the design specification dataset; encrypting the confidential design specification data to produce encrypted confidential design specification data; generate a first encryption key to be associated with the encrypted confidential design specification data; retrieving a confidential design specification data subset for replacing a design element subset with a security hard macro (SHM) placeholder design element set; generating a security hard macro (SHM) placeholder feature set comprising those security hard macro (SHM) placeholder features representing mappings from the confidential design specification data subset to the SHM placeholder design element set; and transmitting, to the first untrusted computing device, the encrypted confidential design specification data, the first encryption key, and the SHM placeholder feature set.

Method, apparatus and computer program product for protecting confidential integrated circuit design

Methods and integrated circuit architectures for assuring the protection of intellectual property between third party IP providers, system designers (e.g., SoC designers), fabrication entities, and assembly entities are provided. Novel design flows for the prevention of IP overuse, IP piracy, and IC overproduction are also provided. A comprehensive framework for forward trust between 3PIP vendors, SoC design houses, fabrication entities, and assembly entities can be achieved, and the unwanted modification of IP can be prevented.

Comprehensive framework for protecting intellectual property in the semiconductor industry

Embodiments of the present disclosure provide methods, apparatus, systems, computing devices, computing entities for setting deprocessing parameters used in conducting hardware deprocessing on a hardware. In accordance with one embodiment, a method is provided that includes: receiving sample images using different E-beam voltages, wherein each image is captured from a backside of the hardware using a different E-beam voltage; generating thickness-based contour maps, wherein each map is generated for an image and includes contour lines indicating locations having a same thickness of remaining material; generating estimated E-beam penetration depths, wherein each depth is generated for an image and is based at least in part on the E-beam voltage used to capture the image; generating an estimated thickness measurement of the remaining material based at least in part on the contour maps and the penetration depths; and setting the deprocessing parameters based at least in part on the estimated thickness measurement.

Hardware deprocessing using voltage imaging for hardware assurance

There is a need for more effective and efficient printed circuit board (PCB) design. This need can be addressed by, for example, solutions for performing automated PCB component estimation. In one example, a method includes identifying a plurality of initial component estimations for the PCB; performing a shadow detection segmentation using the plurality of initial component estimations, a non-direct-lighting image, and one or more direct-lighting images to generate a first set of detected PCB components; performing a super-pixel segmentation using the plurality of initial component estimations and the non-direct-lighting-image to generate a second set of detected PCB components; and generating a bill of materials for the PCB based at least in part on the first set of detected PCB components and the second set of detected PCB components.

Techniques for printed circuit board component detection

A pyramid structure to mitigate optical probing attacks in ICs by scrambling the measurements reflected by a laser pulse is disclosed. The pyramid structure is applied to selected areas at the bottom surface of the metal traces in metal layer to circumvent the extra silicon layer and thus minimize the changes to the conventional device structures. The pyramid structure includes randomized pyramids at nanometer scale. Optical simulation results show the pyramidized metal surface is able to prevent optical probing attacks. The fabrication of pyramids is CMOS compatible as well. Optical simulations are performed to analyze the impact these nano-scaled pyramids in a laser voltage probing attacking model. The nanopyramid can disturb the optical measurements enough to make the attacks practically infeasible. In addition, the nanopyramid structure countermeasure works in a passive mode without consuming any energy.

Optical scrambler with nano-pyramids

Various examples are provided related to power side-channel vulnerability assessment. In one example, a method includes identifying target registers in an IC design; generating input patterns associated with a target function that can generate a power difference in the target registers when processing the target function; determining a side-channel vulnerability (SCV) metric using the power difference produced by the input patterns; and identifying a vulnerability in the IC design using the SCV metric. Identification of the vulnerability allows for modification of the IC design at an early stage, which can avoid power side-channel attacks (e.g., DPA and CPA) in the fabricated IC design. The method can be used for pre-silicon power side-channel leakage assessment of IC designs such as, e.g., cryptographic and non-cryptographic circuits.

CAD framework for power side-channel vulnerability assessment

There is a need for more effective and efficient printed circuit board (PCB) design. This need can be addressed by, for example, solutions for performing automated PCB component estimation. In one example, a method includes identifying a PCB image of a PCB; performing chromaticity-based background subtraction on the PCB image to generate a background-subtracted PCB image; performing morphological noise removal on the background-subtracted PCB image to generate a noise-removed PCB image; and performing object localization on the noise-removed PCB image to identify one or more PCB component estimations within the noise-removed PCB image.

Image processing for printed circuit board component detection

Disclosed are various embodiments for detecting hardware Trojans through information flow security verification. A file comprising register transfer level (HDL) code for an intellectual property core is loaded from memory. An asset within the intellectual property core is identified. An integrity verification or confidentiality verification of the HDL code that represents the asset is performed. An integrity violation or confidentiality violation within the HDL code as a result of performance of the integrity verification or confidentiality violation on the HDL code that represents the asset is detected. A malicious control point or a malicious observation point linked to the asset is identified. Finally, a trigger circuit for a hardware Trojan is identified in response to identification of the malicious control point or malicious observation point.

Hardware trojan detection through information flow security verification

A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a &#x3c6;-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the &#x3c6;-bit protected Obfuscation Key generated by the LFSR, and output k&#x2514;&#x3c6;&#xd7;&#x3b1;&#x2518;-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.

Growing community of inventors

Gainesville, FL, United States of America

Mark M Tehranipoor