Xilinx, Inc.

Mark M Ng

Jesse H Jenkins, Iv

Brian D Erickson

A power control output circuit for a PLD that allows the PLD to selectively operate in either a low current (&ldquo;normal&rdquo;) output mode, or a high current power control mode. In one embodiment, the power control output circuit is incorporated into a special Input/Output Blocks (PC-IOB) of the PLD. When no power control function is needed, a high current output portion of the power control output circuit is deactivated by storing an associated data value a power control configuration memory cell of the PLD, and an output driver of the PC-IOB generates low current output signals on a device I/O terminal. To perform power control functions, a portion of the PLD's programmable logic circuitry is configured to generate a power control data signal, and the high current output portion of the power control output circuit is enabled by storing a corresponding data value in the power control configuration memory cell. When the power control data signal is generated while in the high current power control mode, the high current output circuit turns on a high current transistor that generates a high current power control output signal at the device I/O terminal.

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San Jose, CA, United States of America

Mark M Ng