Nintendo Co., Ltd.

Ati Technologies Ulc

Ati Technologies Inc.

Microsoft Technology Licensing, LLC

Silicon Graphics, Incorporated

Advanced Silicon Technologies LLC

Mark M Leather

Eric Demers

Timothy J Van Hook

Robert A Drebin

Farhad Fouladi

Patrick Y Law

Howard H Cheng

Robert J Moore

John Stephen Montrym

Mark Stefan Grossman

James L Foran

Matthew Komsthoeft

Edward C Chen

Mark G Segal

Chi-Shung Wang

Yoshitaka Yasumoto

Anthony P DeLaurier

A graphics processing circuit includes at least two pipelines operative to process data in a corresponding set of tiles of a repeating tile pattern, a respective one of the at least two pipelines operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. A graphics processing method includes receiving vertex data for a primitive to be rendered; generating pixel data in response to the vertex data; determining the pixels within a set of tiles of a repeating tile pattern to be processed by a corresponding one of at least two graphics pipelines in response to the pixel data, the repeating tile pattern including a horizontally and vertically repeating pattern of square regions; and performing pixel operations on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines.

Dividing work among multiple graphics pipelines using a super-tiling technique

The present invention relates to a rasterizer interpolator. In one embodiment, a setup unit is used to distribute graphics primitive instructions to multiple parallel rasterizers. To increase efficiency, the setup unit calculates the polygon data and checks it against one or more tiles prior to distribution. An output screen is divided into a number of regions, with a number of assignment configurations possible for various number of rasterizer pipelines. For instance, the screen is sub-divided into four regions and one of four rasterizers is granted ownership of one quarter of the screen. To reduce time spent on processing empty times, a problem in prior art implementations, the present invention reduces empty tiles by the process of coarse grain tiling. This process occurs by a series of iterations performed in parallel. Each region undergoes an iterative calculation/tiling process where coverage of the primitive is deduced at a successively more detailed level.

Method and apparatus for rasterizer interpolation

The present invention is a unified shader unit used in texture processing in graphics processing device. Unlike the conventional method of using one shader for texture coordinate shading and another for color shading, the present shader performs both operations. The unified shader uses the same precision for both texture coordinate and color shading, thus simplifying the complexity of programming for two separate conventional shaders with different levels of precision. Furthermore, the present invention uses enhanced scheduling logic to perform indirect texture and bump mapping in a single first-in, first-out (FIFO) memory structure and avoids the problems associated with large FIFOs with buffer registers found in conventional shaders. In one embodiment, a plurality of ALU-memory pairs are synchronized to form a plurality of pipelines to execution shading instructions. In another embodiment, a plurality of unified shaders are synchronized and connected together to processing shading operations concurrently.

Unified shader

The present invention relates to a parallel pipeline graphics system. The parallel pipeline graphics system includes a back-end configured to receive primitives and combinations of primitives (i.e., geometry) and process the geometry to produce values to place in a frame buffer for rendering on screen. Unlike prior single pipeline implementation, some embodiments use two or four parallel pipelines, though other configurations having 2^n pipelines may be used. When geometry data is sent to the back-end, it is divided up and provided to one of the parallel pipelines. Each pipeline is a component of a raster back-end, where the display screen is divided into tiles and a defined portion of the screen is sent through a pipeline that owns that portion of the screen's tiles. In one embodiment, each pipeline comprises a scan converter, a hierarchical-Z unit, a z buffer logic, a rasterizer, a shader, and a color buffer logic.

Parallel pipeline graphics system

The embodiments of the present invention are a method and apparatus to perform anti-aliasing using multi-sampling on a non-power-of-two pixel grid. Using the present invention with 6 sample multisampling gives the same visual antialiasing quality as 8 samples using a prior art technique but uses less memory. A non-power-of-two equally spaced sample from a conventional grid of size N&#xd7;N, where N is 12 can be chosen using the present invention. A scan conversion to determine the set of pixels covered by a polygon is performed in two parts. According to one embodiment, the present invention can multiply and divide by 'N' in order to multisample an image using samples per pixel chosen from a N&#xd7;N sub-sample grid, where 'N' is not necessarily a power of 2. The present invention performs the divide by &#x201c;N&#x201d; step, where the step is achieved using a quick divide by 3 or 12 technique.

Method and apparatus for sampling on a non-power-of-two pixel grid

A graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. A copy pipeline is provided which converts the data from one format to another format prior to writing the data to the external location. The conversion may be from one RGB color format to another RGB color format, from one YUV format to another YUV format, from an RGB color format to a YUV color format, or from a YUV color format to an RGB color format. MPEG image data initially stored in main memory in a YUV format as a texture is transferred to the embedded frame buffer prior to initiating a copy-out process via the copy pipeline from the embedded frame buffer to an external frame buffer in main memory. During the copy-out process, pixels are converted from YUV format to an RGB format. A new texture image containing MPEG image data is placed in the embedded frame buffer prior to each successive copy out process operation so as to produce a streaming video image as a surface texture on at least a portion of a displayed object image.

Graphics system with copy out conversions between embedded frame buffer and main memory for producing a streaming video image as a texture on a displayed object image

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. Emboss style effects are created using fully pipelined hardware including two distinct dot-product computation units that perform a scaled model view matrix multiply without requiring the Normal input vector and which also compute dot-products between the Binormal and Tangent vectors and a light direction vector in parallel. The resulting texture coordinate displacements are provided to texture mapping hardware that performs a texture mapping operation providing texture combining in one pass. The disclosed pipelined arrangement efficiently provides interesting embossed style image effects such as raised and lowered patterns on surfaces.

Method and apparatus for efficient generation of texture coordinate displacements for implementing emboss-style bump mapping in a graphics rendering system

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics pipeline renders and prepares images for display at least in part in response to polygon vertex attribute data and texel color data stored as a texture images in an associated memory. An efficient texturing pipeline arrangement achieves a relatively low chip-footprint by utilizing a single texture coordinate/data processing unit that interleaves the processing of logical direct and indirect texture coordinate data and a texture lookup data feedback path for 'recirculating' indirect texture lookup data retrieved from a single texture retrieval unit back to the texture coordinate/data processing unit. Versatile indirect texture referencing is achieved by using the same texture coordinate/data processing unit to transform the recirculated texture lookup data into offsets that may be added to the texture coordinates of a direct texture lookup. A generalized indirect texture API function is provided that supports defining at least four indirect texture referencing operations and allows for selectively associating one of at least eight different texture images with each indirect texture defined. Retrieved indirect texture lookup data is processed as multi-bit binary data triplets of three, four, five, or eight bits. The data triplets are multiplied by a 3&#xd7;2 texture coordinate offset matrix before being optionally combined with regular non-indirect coordinate data or coordinate data from a previous cycle/stage of processing. Values of the offset matrix elements are variable and may be dynamically defined for each cycle/stage using selected constants. Two additional variable matrix configurations are also defined containing element values obtained from current direct texture coordinates. Circuitry for optionally biasing and scaling retrieved texture data is also provided.

Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system

Apparatus and example methods for environment-mapped style of bump-mapping (EMBM) are provided that use a pre-computed bump-map texture accessed as an indirect texture along with pre-computed object surface normals (i.e., the Normal, Tangent and Binormal vectors) from each vertex of rendered polygons to effectively generate a new perturbed Normal vector per vertex. The perturbed new Normal vectors are then used to look up texels in an environment map. A specialized bump map texture data/coordinate processing 'bump unit' is provided in the graphics pipeline for performing predetermined matrix multiplication operations on retrieved lookup data from the indirect-texture bump map.

Method and apparatus for environment-mapped bump-mapping in a graphics system

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. A copy pipeline is provided which converts the data from one format to another format prior to writing the data to the external location. The conversion may be from one RGB color format to another RGB color format, from one YUV format to another YUV format, from an RGB color format to a YUV color format, or from a YUV color format to an RGB color format. The formatted data is either transferred to a display buffer, for use by the video interface, or to a texture buffer, for use as a texture by the graphics pipeline in a subsequent rendering process.

Graphics system with copy out conversions between embedded frame buffer and main memory

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. A relatively low chip-footprint, versatile texture environment (TEV) processing subsystem is implemented in a pipelined graphics system circulates computed color and alpha data over multiple texture blending/shading cycles (stages). The texture-environment subsystem combines per-vertex lighting, textures and constant (rasterized) colors to form computed pixel color prior to fogging and final pixel blending. Blending operations for color (RGB) and alpha components are independently processed by a single sub-blend unit that is reused over multiple processing stages to combine multiple textures.

Recirculating shade tree blender for a graphics system

The present invention relates to a selectable multi-performance configuration. Instead of the traditional methods of producing separate high-end and low-end graphics chips, the present invention produces processing systems in a single unit. The single unit is readily and functionally partitionable. Each partition is capable of independent operation. By using all of the partitions a high-end graphics processing system may be simulated and tested. By using a subset of the partitions, a low-end graphics processing system may be simulated on the same system without the added cost of re-design of either hardware or software.

Selectable multi-performance configuration

A hardware-accelerated recirculating programmable texture blender/shader arrangement circulates computed color and alpha data over multiple texture blending/shading cycles (stages) to provide multi-texturing and other effects. Up to sixteen independently programmable consecutive stages, forming a chain of blending operations, are supported for applying multiple textures to a single object in a single rendering pass.

Growing community of inventors

Saratoga, CA, United States of America

Mark M Leather