Sambanova Systems, Inc.

Oracle America, Inc.

Oracle International Corporation

Sun Microsystems, Inc.

Mark Luttrell

Manish K Shah

Gregory Frederick Grohoski

Raghu Prabhakar

Ram Sivaramakrishnan

Robert T Golla

Sumti Jairath

Paul Joseph Jordan

David Brian Jackson

Pramod Nataraja

Yuan C Chou

Paul N Loewenstein

David Alan Koeplinger

Mingran Wang

Yongning Sheng

Zeid Hartuon Samoail

Michael D Snyder

William Havinden Bridge, Jr

Kin Hing Leung

Ravinder Kumar

John D Pape

Ramaswamy Sivaramakrishnan

Matthew B Smittle

Zoran Radovic

Ranen Chatterjee

Jared Smolens

David Smentek

Xiaoyan Li

Matthew Thomas Grimm

Xiang Shan Li

Serena Leung

Greg F Grohoski

A reconfigurable data processor comprises an array of configurable units and a bus system. The bus system is connected to the array of configurable units. The bus system includes a top level network and an array level network. The top level network is connected to an external data interface for communication with memory outside of the array of configurable units. The array level network is connected to configurable units in the array of configurable units.

Top level network and array level network for reconfigurable data processors

A tile of an embodiment of a coarse-grain reconfigurable architecture (CGRA) is based on an array of fused compute-memory units (FCMUs), pattern memory units (PMUs), and/or pattern compute units (PCUs) arranged in two dimensions, M×N. Unless clearly noted from context, any reference to a FCMU, PCU, or PMU may refer to one or more of the other units. The communication between a set of FCMUs is performed over a (M+1)×(N+1) switch fabric called the array-level network (ALN) where each switch has connections to its neighboring FCMUs and to neighboring switches in each of the four directions.

Dynamic destination id in an array level network of a reconfigurable dataflow processor

A method comprises a Dynamic Equality of Service (DEoS) arbiter of a switch computing port DEoS metrics based on dynamic input activity of source nodes into input ports of the switch. Based on the port DEoS metrics, the arbiter selects an input port of the switch to make a through-connection to an output port of the switch. The port DEoS metrics can be based on node DEoS metrics including DEoS counters, and/or quantization ranges of DEoS counters, associated with the source nodes. A switching apparatus comprises a switch, a plurality of nodes coupled to the switch, and a DEoS arbiter. The switching apparatus can further comprise a first and second DEoS counter. The DEoS arbiter can perform operations of the method to arbitrate among input ports of the switch to make a through-connection.

Dynamic equality of service in a switch network

A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. A configuration unload controller connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to a plurality of the configurable units in the array to unload the unit files particular to the corresponding configurable units, the unit files each comprising a plurality of ordered sub-files, receiving sub-files via the bus system from the array of configurable units, and assembling an unload configuration file by arranging the received sub-files in memory according to the configurable unit of the unit file of which the sub-file is a part, and the order of the sub-file in the unit file.

Efficient deconfiguration of a reconfigurable data processor

A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

Runtime patching of configuration files

A reconfigurable data processor includes a plurality of configurable units, and a configuration controller. The configuration controller is configured to start execution of a first application graph in a first set of configurable units. Then, concurrently with the execution of the first application graph in the first set of configurable units, the configuration controllers receive a command to load a configuration file into a second set of configurable units and obtain the configuration file. The configuration file contains information to configure the second set of configurable units to execute a second application graph. The configuration file is then loaded into the second set of configurable units and execution of the second application graph is started in the second set of configurable units.

Independent control of multiple concurrent application graphs in a reconfigurable data processor

A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.

Configuration of a reconfigurable data processor using sub-files

A functional unit for a data processor comprises an input register to store a variable X; a first circuit, having an input connected to the input register and an output, to generate a value eon its output; a second circuit, having an input connected to the input register and an output, to generate an output which is a value (tan h(X/2)+1)/2 on its output; a comparator, having an input connected to the input register and an output, to generate a line on its output based on a comparison between X and a constant; and a selector to select between inputs connected to the outputs of the first circuit and the second circuit, in response to the output of the comparator, and provide an output representing a value sigmoid(X).

Sigmoid function in hardware and a reconfigurable data processor including same

A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.

Virtualization of a reconfigurable data processor

Configuration unload of a reconfigurable data processor

Herein are disclosed computation units for element approximation. A computation unit may include a first circuit to compute a first projection &#x3c0; of an input element xfrom a first range to a second range. In the first circuit, the input element xmay have a first format and the projected element ymay have a second format. In addition, in the first circuit, the second format may have more bits than the first format. The computation unit may further include a second circuit operatively coupled to the first circuit to produce a reduction zin the first format using the projected element yin the second format. The computation unit may also include a third circuit operatively coupled to the second circuit to compute a second projection &#x3c1; of the reduction zfrom the second range to the first range to produce an approximation w.

Computational units for element approximation

A system is disclosed, including a plurality of access units, a plurality of circuit nodes each coupled to a respective access unit, and a plurality of data processing nodes each coupled to a respective access unit. A particular data processing node may be configured to generate a plurality of data transactions. The particular data processing node may also be configured to determine an availability of a coupled access unit. In response to a determination that the coupled access unit is unavailable, the particular data processing node may be configured to halt a transfer of the plurality of data transactions to the coupled access unit and assert a halt indicator signal. In response to a determination that the coupled access unit is available, the particular data processing node may be configured to transfer the particular data transaction to the coupled access unit.

Distributed fairness protocol for interconnect networks

Configuration load of a reconfigurable data processor

A configurable circuit configurable according to the data width of elements of a matrix is described that includes a memory array, logic to write a matrix to the memory array having elements with a data width which can be specified using configuration data, logic for a transpose read of the matrix as-written and logic for normal read of the matrix as-written. The memory array includes first and second read ports operable in parallel. Transpose read logic and normal read logic can be coupled to the first and second read ports, respectively, allowing transpose and normal read of a matrix simultaneously.

Matrix normal/transpose read and a reconfigurable data processor including same

Growing community of inventors

Cedar Park, TX, United States of America

Mark Luttrell