International Business Machines Corporation

Mark Louis Ciacelli

Chuck Hong Ngai

Dennis P Cheney

James Wilson Bishop

Gregory Robert Klouda

Stefan P Jackowski

Jack Lawrence Kouloheris

Steven Bradford Herndon

John Edward Fetkovich

Patrick W Gallagher

Wai Man Lam

Robert D Siegl

John William Urda

John David Myers

Apparatus, method and computer program product are provided for digitally processing an encrypted data stream scrambled, for example, according to content scrambling system (CSS) technology. This digital processing insures against communication of clear data within the computer system from a central processing unit (CPU) to any accessible structure, such as memory or a system bus. Descrambling of the (CSS) scrambled data stream occurs within a module executing on the CPU, which is followed by reencryption of the data prior to transfer from the CPU. By so processing the data, integrity of copyrighted material is maintained, while allowing for software descrambling of the CSS encrypted data stream. Various techniques for establishing the encryption/decryption algorithm pair employed are described. Decryption of the re-encrypted data can occur at a receiving software module and/or a receiving hardware device, such as a decoder.

Apparatus, method and computer program product for protecting copyright data within a computer system

An address generation engine is disclosed for a digital video decoder unit coupled to memory in a digital video decoder system wherein the memory accommodates multi-format and/or reduced video data storage. The address generation engine includes a processor and address generation hardware. The processor, coupled to access encoded data to be decoded by the digital video decoder unit, has microcode for deriving from the encoded data relative location information including a vertical component and a horizontal component. The address generation hardware includes a row address register and a column address register for receiving the vertical component and horizontal component, respectively, derived by the processor. The address generation hardware is configured for generating from the vertical component and the horizontal component either a macroblock write address for writing a reconstructed macroblock of data to memory, a motion compensation read address for accessing pertinent motion vector information of the encoded data for reconstructing the macroblock, and a pan and scan offset address usable by a display unit for displaying reconstructed video data in pan and scan format.

Multi-format reduced memory MPEG decoder with hybrid memory address

Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. This is accomplished with a minimum of DRAM demand through the use of a Spill Buffer.

Memory management for an MPEG2 compliant decoder

In a hierarchical, multi-level storage system, recovery from intermittent storage hardware failures is supported by establishing hardware checkpoints at storage system interfaces and by duplication of subsystem hardware within units of the storage system. When error is detected at an interface, all levels of the storage system are quiesced and backed up to a point preceding the occurrence of the error. If a hardware failure causes an error, the system is quiesced while the failed hardware is reconfigured with control logic copied from duplicate hardware. A single restart command restarts system operation.

Error windowing for storage subsystem recovery

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Endicott, NY, United States of America

Mark Louis Ciacelli