Nxp Usa, Inc.

Nxp B.v.

Mark Lehmann

Xiankun Jin

Douglas Alan Garrity

Kumar Abhishek

Hubert Martin Bode

Xianghua Shen

Sebastian Raschbacher

Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.

Testing of on-chip analog-mixed signal circuits using on-chip memory

Body text indent&#x2014;does not have paragraph numbering turned on. Not needed in the Abstract. An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.

Analog-to-digital converter (ADC) testing

An integrated circuit, can comprise a first power supply terminal configured to supply a first voltage, a second power supply terminal configured to supply a second voltage, a first supply monitor including a detector having a first input and a second input, and configured to provide a fault indicator based on a comparison between the first and second inputs, and switching circuitry configured to during a normal operating mode, couple a voltage derived from the first voltage to the first input and a voltage derived from the second voltage to the second input, and during a self-test mode, couple the voltage derived from the second voltage to the first input and the voltage derived from the first voltage to the second input.

Devices and methods for voltage supply monitoring

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Munich, Germany

Mark Lehmann