Imagination Technologies Limited

Mark Landers

Martin John Robinson

Ian King

Michael John Livesley

Alistair Goudie

A converter module handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

Handling memory requests

An on-chip cache is described which receives memory requests and in the event of a cache miss, the cache generates memory requests to a lower level in the memory hierarchy (e.g. to a lower level cache or an external memory). Data returned to the on-chip cache in response to the generated memory requests may be received out-of-order. An instruction scheduler in the on-chip cache stores pending received memory requests and effects the re-ordering by selecting a sequence of pending memory requests for execution such that pending requests relating to an identical cache line are executed in age order and pending requests relating to different cache lines are executed in an order dependent upon when data relating to the different cache lines is returned. The memory requests which are received may be received from another, lower level on-chip cache or from registers.

Executing memory requests out of order

A processor and a method of obtaining data for a processor are provided. The processor comprises at least a first core, a second core, and a distributed cache. The distributed cache comprises a first cache slice connected to the first core and a second cache slice connected to the second core and to the first cache slice. The first cache slice is configured to receive a memory access request from the first core and forward the memory access request to the second cache slice.

Distributed system level cache

A memory interface for interfacing between a memory bus and a cache memory. A plurality of bus interfaces are configured to transfer data between the memory bus and the cache memory, and a plurality of snoop processors are configured to receive snoop requests from the memory bus. Each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.

Memory interface having multiple snoop processors

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

A coherency manager for receiving snoop requests addressed in a physical address space, the snoop requests relating to a cache memory addressable using a virtual address space, the cache memory having a plurality of coherent cachelines, the coherency manager comprising: a reverse translation module configured to maintain a mapping from physical addresses to virtual addresses for each coherent cacheline held in the cache memory; and a snoop processor configured to: receive a snoop request relating to a physical address; in response to the received snoop request, determine whether the physical address is mapped to a virtual address in the reverse translation module; and process the snoop request in dependence on that determination.

Data coherency manager with mapping between physical and virtual address spaces

A memory interface for interfacing between a memory bus and a cache memory, comprising: a plurality of bus interfaces configured to transfer data between the memory bus and the cache memory; and a plurality of snoop processors configured to receive snoop requests from the memory bus; wherein each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.

A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising: a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and a coherency manager comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space; wherein the memory interface is configured to: receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space; translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus; receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and translate the snoop request, at the coherency manager, to a translated snoop request addressed in the virtual address space for processing in connection with the cache memory.

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Hartwell, United Kingdom

Mark Landers