Intel Corporation

Mark Lalich

Subbarao S Vanka

Prasanna Rupasinghe

Bruce A Young

Nicholas D Wade

Abid Ahmad

A method for guaranteeing access to a bus master for reads of main memory in a bridge circuit for joining a host processor, main memory, and a PCI bus, by detecting a read with data posted in the posted write buffer, disabling the posted write buffer, disabling access by the host processor for a selected period, detecting the presence of a retry of the read access, and enabling the posted write buffer after detecting an idle bus for the passage of the preselected time.

Method and apparatus for providing deterministic read access to main

A dynamic cache coherency method and apparatus providing enhanced microprocessor system performance are described. The method and apparatus are advantageously utilized in a microprocessor system comprising a central processing unit (CPU), a write back cache memory, dynamic random access memory (DRAM) main memory, a cache and DRAM controller (CDC), and a data path unit (DPU) with a write buffer. In accordance with the method of operation, following a write access by the CPU, the CDC determines whether the write buffer is full and whether the cache line associated with this access has been modified, i.e. is 'clean' or 'dirty.' In the event that the write buffer is full, or the cache line is dirty, the write operation proceeds in accordance with a write back mode of operation. However, if the write buffer in the DPU is not full, and the cache line is clean, the CDC writes the write data to both the cache line in cache memory, and the write buffer in the DPU. These two write operations proceed concurrently, and are completed in the same amount of time. When they are completed, the processor cycle is also complete, and the CPU proceeds with its next task. Thereafter, in the background, the posted data in the write buffer is flushed to DRAM, without incurring any CPU overhead.

Dynamic cache coherency method and apparatus using both write-back and

A concurrent cache line replacement method and apparatus for a high performance microprocessor system with a write-back cache memory is disclosed. The invention is advantageously utilized in a microprocessor system comprising a CPU, a write back cache memory, DRAM main memory, a cache and DRAM controller (CDC), and a data path unit (DPU) with a write buffer capability. In accordance with the method of operation of the present invention, when a read access by the CPU results in a cache miss to a dirty cache line, the CDC concurrently initiates two operations. The CDC initiates the writing of the dirty line in the cache memory to a write buffer in the DPU, while concurrently, the CDC also initiates the reading of the new line from the DRAM main memory. With respect to the writing of the old line from cache memory to the write buffer in the DPU, at some time subsequent to the initiation of this operation, the CDC completes the writing of the old line to the DPU and internally notes this completion, and at a later point in time, the CDC is able to transfer of the old line from the write buffer in DPU to the DRAM. With respect to the reading of the new line from the DRAM main memory, initiated concurrently with the preceding write operation, this read operation overlaps in time with the single restriction that the CDC not cause the new line to actually be written to the cache memory until the writing of the old line to the write buffer in the DPU is completed. Alternatively, the restriction can be tailored to apply at the d-word level.

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Orangevale, CA, United States of America

Mark Lalich