Motorola Corporation

Mark L Shaw

Ronald J Freimark

Howard F Weber

This invention relates to the use of a multiplexing technique to allow for the unambiguous enabling of remotely located receiving devices. In particular, a plurality of pushbutton switches, each capable of controlling a distinct function, has a common node whose output is transmitted through the single slip-ring usually found on the steering column of an automotive vehicle. This slip-ring is normally used to conduct an electrical voltage from the horn ring to the horn control relay independent of the position of the steering wheel. The multiplexing technique disclosed herein allows for separate and independent control of not only the horn but also other functions such as a cruise control using the existing single slip-ring as the mechanism to transmit the desired signal commands. The demultiplexed signals are derived from logic circuitry located at the distal point of the slip-ring assembly.

Auxiliary steering wheel command system

An amplifier circuit is disclosed for temperature compensating the output voltage thereof with respect to undesirable temperature induced signals from a silicon pressure transducer and/or from components of the amplifier itself. The amplifier includes a first operational amplifier and a second operational amplifier. A first circuit connects the output terminal of the first operational amplifier through a summing node to one input terminal of the second amplifier. Output signals from the pressure transducer are applied between one input terminal of the first operational amplifier and another input terminal of the second amplifier. A temperature compensating circuit is connected to the summing node for enabling the output voltage of the amplifier to be substantially independent of temperature. An initial offset voltage compensating circuit is coupled to the summing node for adjusting the intercept of the pressure-to-output voltage transfer curve. The gain of the second operational amplifier determines the slope of the curve.

Temperature compensating pressure sensor amplifier circuits

A digital frequency quadrupler which provides output pulses at a rate equal to four times the number of input pulses. The input frequency range is extended by logic which allows additional pulses to be inserted in the output as the input frequency increases causing overlap between adjacent pulses. When the maximum upper range limit is reached the quadrupler saturates, that is, the output frequency becomes constant.

Digital frequency quadrupler

A digital speed control system includes a first binary up-counter called an Actual Count Register. The Actual Count Register is initially reset to contain all '0''s. During a sample time, an input is applied to the Actual Count Register so that it counts up to a first binary number during the sample time. The first binary number represents a reference speed. The system includes a Reference Count Register. In response to read and store command, the first binary number is loaded into the Reference Count Register, where it remains until the next request for a new reference speed. The system further includes a first binary presettable up-counter called the Error Register. The Error Register counts up at the same rate and in response to the same count signal as the Actual Count Register. During a Transfer signal which follows the Read signal, the complement of the first binary number is transferred from the Reference Count Register into the Error Register. The system also includes a second binary presettable up-counter called an Acceleration Register. The inputs of the Acceleration Register are coupled to the outputs of the Actual Count Register so that during the transfer signal the complement of the first binary number is loaded into the Acceleration Register. A decoder connected to the outputs of the Error Register interprets its contents, and a second decoder interprets the contents of the the Acceleration Register.

Digital speed control system

A digital speed control system includes a first binary up-counter called an Actual Count Register. The Actual Count Register is initially reset to contain all '0''s. During a sample time, an input is applied to the Actual Count Register so that it counts up to a first binary number during the sample time. The first binary number represents a reference speed. The system includes a Reference Count Register. In response to read and store command, the first binary number is loaded into the Reference Count Register, where it remains until the next request for a new reference speed. The system further includes a first binary presettable up-counter called the Error Register. The Error Register counts up at the same rate and in response to the same count signal as the Actual Count Register. During a Transfer signal which follows the Read signal, the complement of the first binary number is transferred from the Reference Count Register into the Error Register. The system also includes a second binary presettable up-counter called an Acceleration Register. The inputs of the Acceleration Register are coupled to the outputs of the Actual Count Register so that during the transfer signal the complement of the first binary number is loaded into the Acceleration Register. A decoder connected to the outputs of the Error Register interprets its contents, and a second decoder interprets the contents of the Acceleration Register.

A zener diode and resistor network is coupled to a single conductor by a switching device which, in combination with the network, produces a voltage on the conductor representative of one of four commands selected by the switching device. Another zener diode and resistor network is coupled to the receiving end of the transmission conductor and operates to generate two ternary signals which, in combination, are representative of the selected command. A plurality of dual-threshold CMOS logic gates generates four binary output signals responsive to the two ternary signals.

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Mesa, AZ, United States of America

Mark L Shaw