Fairchild Semiconductor Corporation

Mark L Rinehimer

Joseph Andrew Yedinak

Thomas E Grebs

Praveen Muraleedharan Shenoy

John L Benjamin

Gary M Dolny

Hamza Yilmaz

Dean E Probst

James N Pan

Steven Paul Sapp

Christopher Lawrence Rexer

Michael D Gruenhagen

Fred Session

Suku Kim

Sampat Shekhawat

Jaegil Lee

Douglas Joseph Lange

Dwayne S Reichl

Hui Chen

Dan Kinzer

Jon Gladish

Richard Stokes

Ritu Sodhi

Jason Higgs

Rohit Dikshit

Scott Pearson

Rodney S Ridley, Sr

Sungjin Kuen

Tracie Petersen

Harold Heidenreich

Jayson Preece

Chongman Yun

Josph A Yedinak

Christopher L Rexer

In a general aspect, a bridge circuit can include a first bridge including a first plurality of MOSFETs and including a first input terminal and a second input terminal, and a second bridge including a second plurality of MOSFETs and including a third input terminal and a fourth input terminal. The first bridge and the second bridge can be coupled in parallel and being coupled to a first load terminal and a second load terminal.

MOSFET bridge circuit

In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.

Superjunction structures for power devices and methods of manufacture

A power device includes a semiconductor substrate having a plurality of alternately arranged pillars of first and second conductivity types. At least one of the plurality of pillars of second conductivity type includes a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench, a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type.

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

Double layer metal (DLM) power MOSFET

Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

Reduced process sensitivity of electrode-semiconductor rectifiers

Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.

Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same

A structure that includes a rectifier further comprises a semiconductor region of a first conductivity type, and trenches that extend into the semiconductor region. A dielectric layer lines lower sidewalls of each trench but is discontinuous along a bottom of each trench. A silicon region of a second conductivity type extends along the bottom of each trench and forms a PN junction with the semiconductor region. A shield electrode in a bottom portion of each trench is in direct contact with the silicon region. A gate electrode extends over the shield electrode. An interconnect layer extends over the semiconductor region and is in electrical contact with the shield electrode. The interconnect layer further contacts mesa surfaces of the semiconductor region between adjacent trenches to form Schottky contacts therebetween.

Structure with PN clamp regions under trenches

Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.

Trench-shielded semiconductor device

A structure that includes a rectifier is formed as follows. A trench is formed in a semiconductor region of a first conductivity type. A dielectric layer is formed along opposing sidewalls of the trench but is discontinuous along the bottom of the trench. A doped liner is formed over the dielectric layer and along the bottom of the trench. The doped liner includes dopants of a second conductivity type and is in direct contact with the semiconductor region along the bottom of the trench. A portion of the dopants are diffused from the doped liner into the semiconductor region along the bottom of the trench to form a doped region. The doped region forms a PN junction with the surrounding semiconductor region.

Rectifier with PN clamp regions under trenches

A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.

Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off

Growing community of inventors

Mountain Top, PA, United States of America

Mark L Rinehimer