Intel Corporation

Mark L Elzinga

Young Min Park

Jagannadha Rao Rapeta

Surya Musunuri

Robert R Fulton

Nasser A Kurd

Daniel Gruber

Mohamed A Abdelmoneum

Martin Clara

Michael W Altmann

Noam Familia

Dror Lazar

Mohamed Abdelsalam

Vadim Levin

Amr M Lotfy

Michael Bichan

Mamdouh O Abd El-Mejeed

Youngmin Park

The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal.

Transformer, transmitter circuit, semiconductor chip, semiconductor package, base station, mobile device, and method for a radio frequency transmitter

Described is a high Q-factor inductor. The inductor is formed as a unit cell coil, which is copied twice for a dual-coil inductor and copied four times for a quad-coil inductor. For each copy of the unit cell coil, the coil is rotated a subsequent substantially 90 degrees or substantially &#x2212;90 degrees. The rotation enables the terminals of the inductor to be routed equal-distant to a circuit that is placed in the line of symmetry between the two coils.

High Q-factor inductor

Described is an apparatus comprising a first circuitry, a second circuitry, a first capacitor array, and a second capacitor array. The first circuitry may have an oscillator. The first capacitor array may have a set of first capacitors to tune the oscillator. The second capacitor array may have a second capacitor to tune the oscillator. A capacitance of the second capacitor may be greater than an average capacitance of the first capacitors. The second circuitry may be operable to synchronously activate the second capacitor and deactivate a number N of the first capacitors, and to synchronously deactivate the second capacitor and activate the N first capacitors, based on a predetermined sequence.

PLL capacitor swap technique and low jitter dynamic Digital Controlled Oscillator band select

Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

Apparatus and method for extending frequency range of a circuit and for over-clocking and under-clocking

Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.

Apparatus and method for automatic bandwidth calibration for phase locked loop

Apparatus and method for extending frequency range of a circuit and for over-clocking or under-clocking

Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

Apparatus and method for fast phase locking for digital phase locked loop

Disclosed herein are swizzling techniques that may provide capacitive and inductive noise cancellation on a set of signal lines. Positive noise due to a capacitive coupling between attacker signal lines and near victim signal lines is, in part, cancelled by negative noise due to inductive coupling between the attacker signal lines and a far victim signal line. Swizzling patterns and repeatable swizzling patterns are computed to transpose near victim signal lines and far victim signal lines in subsequent segments to facilitate the capacitive and inductive cancellation. The signal lines are optionally reordered by computing a final swizzling to restore the set's original ordering.

Calculating interconnect swizzling patterns for capacitive and inductive noise cancellation

A method and system for determination of the worst case switching vector, which greatly reduces the search space complexity. A single simulation is performed in the time-domain wherein the roles of the victim and attacker conductors are switched. In particular, the search space is reduced by virtue of the fact that certain combinations for the behavior attacker conductors are excluded. Only the phases of the attacker signals need to be determined.

Growing community of inventors

El Dorado, CA, United States of America

Mark L Elzinga