National Semiconductor Corporation

Celerity Research Pte. Ltd.

Novellus Development Company, LLC

Mark L DiOrio

Jeffrey C Demmin

Jon T Ewanich

Vivek B Dutta

Jaime A Bayan

Robert M Hilton

Dzintra Hilton, Legal Representative

Young I Kwon

A probing system for electrical testing of a semiconductor device uses a probe device including probe tips on a surface of a semiconductor die. The probe tips can be fabricated as metal bumps on contact pads having a pattern that is the same as the pattern of contact pads on the semiconductor device. The semiconductor die can provide the probe device with substantially the same thermal properties as the semiconductor device, so that the same probe can be used for testing over a broad temperature range. Further, the probe device can be fabricated using semiconductor device fabrication techniques, so that probe designs can scale down as device fabrication techniques move to smaller dimensions.

Probing system uses a probe device including probe tips on a surface of a semiconductor die

Packaging processes and structures provide thin-film interconnects for high performance signal transmission of high frequency signals. The thin-film interconnects can be formed on a carrier that is at least partly removed for formation of terminals such as a BGA connected to the thin-film interconnects. Removal of the carrier can leave a frame for handling of the thin-film interconnects during subsequent processing. The thin film interconnects can be used to route signals to external terminals, between dies, or between functional units within a die. This allows the dies to contain fewer routing layers and allows configuration of a device such as an ASIC during packaging. A coarser pitch interconnect structure can be fabricated on the carrier using different technology for power and ground management and/or in a core that attaches to the thin-film package structure.

Technology partitioning for advanced flip-chip packaging

A probing system or process for electrical testing of a device fabricated on a wafer also conditions terminals such as solder balls on the device to improve uniformity of the heights of the terminals and improve the reliability of connections to an interconnect substrate in a flip-chip package or to a printed circuit board in a chip-on-board application. The system can employ a probe card that is a printed circuit board and/or is substantially identical to interconnect substrates used in flip-chip packaging. The probe card can be replaceable on a test head to allow for quick changes the reduce ATE downtime and to accommodate device changes such as a die shrink. Probe tips on the probe card can be the contact pads or bumps that are the normal electrical contact structures of the interconnect substrates.

Wafer probing that conditions devices for flip-chip bonding

The planarity of external terminals or a ball grid array on a device package can be improved through use of test probes that flatten the electrical terminals while forming the electrical contacts for package testing. After testing, the package has external terminals with improved planarity that improves the electrical connections formed during assembly of a system containing the package.

Planarizing and testing of BGA packages

A package for containing an integrated circuit component is provided which includes one or more layers with exposed edges surrounding a central opening. The integrated circuit component is positioned in the central opening. Bond wires connect the bond pads of the integrated circuit component to the continuous shelves of the various stepped-back stadium-like layers as well as to individual insulated leads. The layers are spaced apart by beads or columns of insulative material and the major portion of the layers are separated from each other by a gaseous dielectric, preferably air. The R-C constant is reduced and the speed of transmission is increased by the presence of the low dielectric material providing a device which can function rapidly. The stepped portions of the layers are exposed to allow for electrical interconnections within the layers, as well as from each layer to the integrated circuit.

Method of connecting an IC component with another electrical component

A thermally enhanced leadframe having heat conductive paths which thermally couple a die attach pad to thermal connection points spread out as far as possible from each other on the perimeter of the package. The area of the heat conductive path is maximized to occupy substantially all area in the package not occupied by the electrically conductive paths between the wire bond locations and the external connection points such as pins. This configuration maximizes the area of the printed circuit board which is heated thereby increasing thermal cooling efficiency. Further, the leadframe configuration maximizes the area of contact between the integrated circuit package and the heat conductive path thereby increasing the thermal conductivity between the device junctions on the integrated circuit die and the ambient through the material of the package itself.

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Cupertino, CA, United States of America

Mark L DiOrio