Texas Instruments Corporation

Dialogic Corporation

Mark L Buser

Jeff L Hunter

Imtaz Ali

Gilbert Laurenti

Bruce W C Lee

Shigeshi Abiko

Eric Ponsot

Douglas E Deao

Marc Couvrat

Jean-Pierre Giacalone

Eric L Badi

Herve Catan

Armelle Laine

Karim Djafarian

Vincent Gillet

Francois Theodorou

Gael Clave

Jean-Marc Philippe Bachot

Anne Lombardot

Alain Boyadjian

Yves Masse

Walter A Jackson

Ranjan Singh

Jack Rosenzweig

Emmanuel Ego

Laurent Ichard

Jean-Louis Tardieux

David Russell

Frederic Nidegger

N M Ganesh

Ganesh M Nandyal

Bruce Wc Lee

The present invention provides methods for executing instructions in a processor to facilitate the debugging of digital systems. In these methods, a halt identifier field is associated with every instruction that holds an encoding specifying an action to be performed by a processor. As instructions are executed on a processor, actions are performed by the processor based on the value of the halt identifier field of the executed instructions. In an embodiment, when each instruction is executed, the contents of the halt identifier field are compared to a pre-selected identifier value and the processor is halted if the values are the same. In a multiprocessor system, the pre-selected identifier may be a unique value that identifies the processor such that when the halt identifier field is equal to that value, the processor will halt. In a single processor system, the pre-selected value may be used to identify a task, a process, or a thread of execution that is to be halted when a halt identifier field with that value is encountered.

Software breakpoints with tailoring for multiple processor shared memory or multiple thread systems

Systems and methods of adjusting synchronization of audio media streams and video media streams in 3G mobile communications systems that can mitigate the effects of temporal skew due to intervening processing elements associated with media channels carrying the respective media streams. The systems and methods are operative to adjust the synchronization of audio media streams and video media streams by receiving control messages that report delays due to such intervening processing elements, calculating a relative amount of delay using the reported delays for each media channel, and applying a delay factor based on the relative amount of delay to the faster media channel to place the audio media streams and the video media streams in proper temporal alignment. The delay factor is applied to the faster media channel at those locations within the mobile communications systems where the audio and video media streams are combined and/or separated for subsequent transmission.

Adjusting audio and video synchronization of 3G TDM streams

The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software memory map representing the memory usage of the processors in the system to be debugged is created and in the software memory map is an indication of whether or not each processor has a cache. At least two debug sessions associated with two processors are activated. If an active debug session requests a write to a shared memory location, the request is executed and the software memory map is searched to located all processors having read access to that shared memory location. The write request is broadcast to each of the located processors so that each processor can perform any required cache updates.

Software shared memory bus

The invention relates to a method for transparently writing to shared memory when debugging a multiple processor system. In this method, a software memory map reflecting the memory usage of the processors in the system to be debugged is created. Two or more debug sessions associated with processors in the system are activated. When a debug session makes a write request to a shared memory location, a check is made to see if the processor associated with that debug session has write access to the shared memory location. If it does, that processor is used to execute the write. If it does not, the software memory map is searched to find a processor that does have write access to the shared memory location and that processor is used to execute the write.

Transparent shared memory access in a software development system

The invention relates to a method for maintaining coherency of software breakpoints in shared memory when debugging a multiple processor system. Using this method, at least two debug sessions associated with processors in the multiple processor system are activated. When a debug sessions sets a software breakpoint in a shared memory location, all active debug sessions are notified that the software breakpoint has been set. And, when a software breakpoint in shared memory is cleared by a debug session, all active debug sessions are notified that the software breakpoint has been removed.

Shared software breakpoints in a shared memory system

Method for maintaining cache coherency in software in a shared memory system

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

A processor ( ) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Instructions may be executed during delay slots after program branching while an execution pipeline is being restarted. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A software breakpoint instruction is provided for debugging purposes. In order to correctly emulate the operation of the instruction pipeline when a software breakpoint instruction is executed during a delay slot, the width ( ) of the software breakpoint is the same as the replaced instruction. A limited number of breakpoint instruction length formats ( ) are combined with non-operational instructions (NOP, NOP ) to form a large number of combination instructions that match any instruction length format.

Various length software breakpoint in a delay slot

A processor ( ) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A trace FIFO ( ) is provided for tracing a sequence of instruction addresses to assist with software or hardware debugging. In order to conserve space, only the addresses of an instruction just before (M&plus;K, P&plus;Q) and just after (P, R) a discontinuity are stored in the trace FIFO. A sequence of instruction lengths (SEC LPC) is also stored in the trace FIFO so that the sequence of instruction addresses can be reconstructed by interpolating between two discontinuity points (P to P&plus;Q).

Trace fifo management

Growing community of inventors

Green Brook, NJ, United States of America

Mark L Buser