National Semiconductor Corporation

Texas Instruments Corporation

Mark Kuhns

Richard Alexander Erhart

Bruce C Moore

Donald E Camp

Christopher A Ludden

Wei Ma

Zhenyong Zhang

Mikko Topi Loikkanen

Arif Alam

Juha Tapani Pennanen

Loren Tomasi

Kevin Vannorsdel

Daniel L Simon

Randy J Dahl

Osama F Alborno

A duty-cycled acoustic sensor saves power, for example, by operating for relatively short periods of time in a repetitive manner. A sensor bias current provides operating power to the sensor. An output analog signal from the sensor carries the information induced by the sensor upon the bias signal. Capacitive coupling is employed to remove direct DC voltage from the output analog signal to generate an analog input signal for acoustic analysis. A capacitor for capacitive coupling is pre-charged to reduce the charging time of the capacitor as the sensor is being powered up. After the capacitor is sufficiently precharged, acoustic analysis is performed on the analog input signal. The sensor is powered down by substantially blocking current flow through the sensor, which saves power. Results of the acoustic analysis can be used, for example, to control parameters of the duty-cycling of the acoustic sensor.

Duty-cycling microphone/sensor for acoustic analysis

A Switch Node Assisted Linear architecture, including a linear amplifier in parallel with a switched converter, is configurable in two tracking modes: (a) a SMAL regulator in which the amplifier sets load voltage with an envelope tracking bandwidth, and the switched converter is configured for current assist, and (b) a Switched Mode Power Supply configuration in which the amplifier is switch-decoupled, and the switcher circuit is switched configured with an output capacitor, operable as an SMPS providing load voltage with an adaptive tracking bandwidth that is less than the envelope tracking bandwidth. Staged switching effects substantially seamless transitions between tracking modes, with the amplifier holding the load voltage at a substantially constant envelope tracking voltage (CVET): (a) for ET-AT transitions, the CVET mode enables pre-charging the output capacitor to a target AT voltage, prior to switch-decoupling the amplifier; and (b) for AT-ET transitions, CVET mode enables discharging the output capacitor.

Switched mode assisted linear regulator with seamless transition between power tracking configurations

An embodiment of the present invention is directed to a circuit including a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency Fand a secondary clock having a frequency F. The primary data is received over a fixed periodic interval Tand at a rate substantially equal to F. The amount of primary data received over Tis known to be N. The data relay stage is further configurable to provide secondary data via a secondary data interface based on the primary data and the secondary clock. The circuit also includes a phase-locked loop (PLL) circuit configurable to receive an interval reference signal having a frequency Fsubstantially equal to 1/T. The PLL circuit is also configurable to provide the secondary clock based on the interval reference signal.

Setting and minimizing a derived clock frequency based on an input time interval

A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.

Numerically controlled oscillator (NCO) output clock phase smoothing

A method and system for digitally scaling a waveform. A method is described performing a linear waveform transformation and translation of a curve in a smooth and continuous fashion. Another method is described for scaling a waveform in which the available accuracy and resolution is manipulated for a given waveform. Specifically, by strategically placing virtual tap points of a waveform, as well as changing the scaling factors used for calculating points on the waveform provides for adjusting the accuracy and resolution in one or more regions of a waveform. These scaling methods provide a digital equivalent of a voltage tap-based analog resistor ladder used for digital-to-analog conversion. The digital virtual tap points represent the analog voltage tap points, and the vertical translation of the curve acts in a smooth, monotonic, and continuous fashion.

Method and system for digitally scaling a gamma curve

Various technologies for efficiently storing and retrieving streaming data are described. Bits of data (e.g., P bits of data) are received and separated into most significant bits (MSB) of data and least significant bits (LSB) of data. Further, the MSB of data and the LSB of data are respectively packed into a first word and a second word. The first word is stored in a first area of a frame buffer and the second word is stored in a second area of the frame buffer. As a result, data is managed in a more efficient way to reduce memory bandwidth requirement.

Methods and systems for efficiently storing and retrieving streaming data

A method of operating a display includes operating a pixel of the display using a first signal to provide a first brightness level. A characteristic of the first signal is represented by a value in a range extending from a minimum signal value to a maximum signal value. A second brightness level is then selected and is different from the first brightness level. A truncated table is consulted and contains overdrive values for selected pairs of possible first and second brightness levels. The overdrive values are in a range extending from a minimum table value to a maximum table value, where the minimum table value is less than the minimum signal value or the maximum table value is greater than the maximum signal value or both. An overdrive signal is determined from the overdrive values of the truncated table based on the first and second brightness levels. The pixel is briefly operated using the overdrive signal to facilitate transition to the second brightness level. The pixel is then operated using a second signal corresponding to the second brightness level.

Methods and systems for determining display overdrive signals

An exemplary point-to-point display system comprises a host system, a timing controller, and a display. The host system is configured to provide data for display. The timing controller is configurable to provide data swapping, bus swapping, bit swapping, and combinations thereof to provide arranged data in response to the provided data. The display is configured to display the arranged data.

Point-to-point display system having configurable connections

A method and circuit capable of handling skew between a clock and data signal up to +/&#x2212; one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first sampling region and in a second sampling region and determining a difference between a number of transitions in the first sampling region and a number of transitions in the second sampling region. The sampling regions and a deskew timing signal may then be incremented or decremented based on a comparison of the computed difference to a predetermined constant. If no transitions occur on a particular bit, the algorithm times out leaving the deskew timing signal in the original position. When analysis of a final bit of a channel is completed, the algorithm begins monitoring and analyzing the first bit of another channel.

Switched deskew on arbitrary data

A false DE rejection system is described. DEs are ignored during a programmable vertical lockout period. Internal timing is used during the vertical lockout period to count the number of vertical lines to ignore. The first DE received after the vertical lockout period signifies the start of the next graphics frame. Default video is output during the vertical lockout period. The TCON is synchronized to the start of the graphics frame. A horizontal line length timer measures the timing for the horizontal line length. The horizontal line length timer may also keep a moving average of all of the lines that it has measured. This helps to ensure that the TCON does not get out-of-sync with the input stream during the vertical blanking periods. The DE rejection system includes automatic blanking detection that ignores DEs that occur after the end of a predetermined graphics frame. The vertical lockout does not occur until there has been no DE for an entire line.

Application and method for rejection of a false data enable signal during vertical blanking periods in a graphics system

The present invention is related to staggering data to reduce noise in a graphics display system. Line-to-line data staggering is achieved by staggering the starting point at which data is transmitted within each line of data. Frame-to-frame staggering is implemented by staggering the starting point of the first line of data from its value in the previous frame by a predetermined value each frame. Alternatively, frame-to-frame data staggering can be performed every other frame instead of every frame.

Method and apparatus for reducing noise in a graphics display system

The present invention provides a point-to-point data bus architecture and a protocol for a graphics system. The TCON transmits the data to the column drivers using separate point-to-point data buses. Data may be transmitted to the column drivers during a horizontal blanking period resulting in more data being written to the column drivers as compared to a typical graphical display system. As each point-to-point data bus contains only the data for its corresponding column driver the instantaneous data rate to any column driver is lower than in conventional multi-drop architectures. The point-to-point system has fewer printed circuit board (PCB) lines and a lower loop area than a conventional multi-drop system. A protocol may also be implemented. The protocol may provide for system level control and coordination of column drivers and other display system components. This protocol allows the TCON to control the operation of the column drivers without the need for extra PCB lines.

Data bus system and protocol for graphics displays

A data/clock deskewing methodology uses a delay-locked loop (DLL) circuit. The DLL circuit generates a number of clock phases in response to an input clock, where each clock phase is delayed relative to the input clock signal. The clock phases are used to sample data from a data line. The sampled data is checked against a preamble pattern (a sequence of known data). A digital deskew control block selects one of the clock phases after analyzing the results of preamble pattern check such that subsequently received data is sampled with the appropriately selected clock phase.

Growing community of inventors

Peoria, AZ, United States of America

Mark Kuhns