Micron Technology Incorporated

Mark K Hadrick

Kang-Yong Kim

Yang Lu

John Christopher Sancon

Hyun Yoo Lee

Dean D Gans

Jeffrey P Wright

Donald M Morgan

Sujeet V Ayyapureddi

Jongtae Kwak

Simon J Lovett

Victor Wong

William F Jones

Keun Soo Song

Yu-Sheng Hsu

Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include a controller with logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

Bank-level self-refresh

Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include a master die and a slave die communicatively coupled to each other through an internal bus. The apparatus can be configured to use an internal command and/or a data clock to coordinate the storage/write operation at the slave die instead of or in addition to a command address clock.

Apparatus with timing control for a die grouping

Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

Self-refresh arbitration

Apparatuses and techniques for implementing a standalone mode are described. The standalone mode refers to a mode in which a die that is designed to operate as one of multiple dies that are interconnected can operate independently of another one of the multiple dies. Prior to connecting the die to the other die, the die can perform a standalone read operation and/or a standalone write operation in accordance with the standalone mode. In this way, testing (or debugging) can be performed during an earlier stage in the manufacturing process before integrating the die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the standalone mode can be executed independent of whether the die is connected to the other die.

Standalone mode

Apparatuses and techniques for implementing a data-transfer test mode are described. The data-transfer test mode refers to a mode in which the transfer of data from an interface die to a linked die can be tested prior to connecting the interface die to the linked die. In particular, the data-transfer test mode enables the interface die to perform aspects of a write operation and output a portion of write data that is intended for the linked die. With the data-transfer test mode, testing (or debugging) of the interface die can be performed during an earlier stage in the manufacturing process before integrating the interface die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the data-transfer test mode can be executed independent of whether the interface die is connected to the linked die.

Data-transfer test mode

Memory devices with half-width data path or data buses clocked by double-pumped strobe signals are disclosed herein. The methods and devices may employ a single delay chain (e.g., a column access strobe (CAS) chain) to perform the double-pumped operations. The delay chain may include multiple delay elements that may generate one or two pulses based on the double-pumped strobe signals. Methods for interfacing, such as read and write methods are also disclosed.

Half-width, double pumped data path

Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

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Boise, ID, United States of America

Mark K Hadrick