Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Clearwire Corporation

Mark Jon Winter

Yifei Zhang

Christopher Gronlund

Myron Buer

Peter Paul Gelbman

Carl A Monzel

Eric Hall

Saket Gupta

Jeffrey Sewell

A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.

Write assist circuit for lowering a memory supply voltage and coupling a memory bit line

Passive write assist passively improves SRAM performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating costs (e.g., power consumption, cooling) associated with active write assist schemes. Passive write assist may be implemented in peripheral circuitry or embedded in an SRAM array or even in each array cell or bitcell. For example, one or more memory cells may be converted to provide passive write assist to a plurality of other memory cells. As another example, each memory cell may independently implement passive write assist using one or more high resistive contacts to couple to the array power supply, resulting in the array voltage level being changed by different amounts in different memory cells according to cell variations.

Passive SRAM write assist

A device for monitoring process variations across memory bitcells includes a bitcell inverter that provides an output voltage to be used for identifying skewed corners of the memory bitcells. A first comparator compares the output voltage with a first reference voltage, and a second comparator compares the output voltage with a second reference voltage. The first and the second comparators generate a corner code based on comparison results.

All voltage, temperature and process monitor circuit for memories

Disclosed is a monitoring system that includes at least one performance monitor integrated into a semiconductor die. The performance monitor comprises at least one ring oscillator that includes a plurality of stages. Each stage comprises at least one memory device. In one embodiment, the performance monitor may also include a setting circuit that has a burn-in input and an enable input. The setting circuit is capable of setting an input signal of the at least one ring oscillator to a reference voltage level. The performance monitor is configured to produce a ring delay that is characterized by a performance of the at least one memory device. The ring delay may be utilized to scale an operating voltage of the at least one memory device on the semiconductor die.

Performance monitor with memory ring oscillator

A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. Further, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.

Low power content-addressable memory

A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.

System for reducing power consumption and increasing speed of content-addressable memory

A subscriber management system for a communication system having a radio access network coupled to by a gateway node to a packet switched network. The system consolidates three prior art subscriber management system components, a DPI device, a QoS Policy Manager, and an Application Manager, into a DPI platform. The system also relocates functions to the DPI platform that were previously provided by the gateway node in prior art networks. Specifically, an Accounting Client, a Hotlining function, and a QoS SFA functionare located to the DPI platform. By consolidating network components and relocating functions to the DPI platform, the number of control interfaces in the network can be reduced. Further, network components produced by different vendors may be integrated more easily. A method of implementing hotlining in the system is also provided.

Growing community of inventors

Seattle, WA, United States of America

Mark Jon Winter