Lsi Logic Corporation

Marvell Asia Pte., Ltd.

Cavium International

Mark Jon Kwong

Tejas Maheshbhai Bhatt

Jason Daniel Zebchuk

Timothy Toshio Nakada

Hong Jik Kim

Gregg Alan Bouchard

Ahmed Shahid

Robert Wayne Moss

David O Sluiter

Christopher M Giles

Peter Korger

M Wesley Schrader

John Lynch

Method and system embodying the method for scheduling arbitration among a plurality of service requestors encompassing: designating among the plurality of service requestors all the service requestors that have an active request; determining whether at least one of the designated service requestors has an un-served status indicator which is set; and when the determining is positive then: selecting one of the at least one designated service requestors in accordance with a pre-determined policy; and clearing the un-served status indicator for the selected service requestor, is disclosed.

Method and apparatus for scheduling arbitration among a plurality of service requestors

Method and system embodying the method for programmable scheduling encompassing: enqueueing at least one command into one of a plurality of queues having a plurality of entries; determining a category of the command at the head entry of each of the plurality of queues; processing each determined non-job category command by a non-job command arbitrator; and processing each determined job category command by a job arbitrator and assignor, is disclosed.

Programmable hardware scheduler for digital processing systems

Method and system embodying the method for load balancing of scheduled jobs among a plurality of engines encompassing determining a number of cluster credits for each of a plurality of clusters that comprise at least one engine capable of processing a scheduled job; determining a number of engine credits for each of the plurality of engines comprising each of the at least one engine in accordance with a number of jobs assigned to each of the plurality of engines; evaluating the determined number of cluster credits and the determined number of engine credits in accordance with a credit evaluation policy; and assigning the job to one of the plurality of engines in accordance with the evaluation, is disclosed.

Method and apparatus for load balancing of jobs scheduled for processing

An apparatus including a plurality of first base circuits, a plurality of second base circuits, a first test circuit, a second test circuit, and a test path. The plurality of first base circuits may be coupled to the plurality of second base circuits via one or more base circuit paths on a layout. The first test circuit may be disposed in a first distal location of the layout. The second test circuit may be disposed in a second distal location of the layout. The test path may be configured to (i) couple the first test circuit to the second test circuit and (ii) generate a test time delay from the first test circuit to the second test circuit incrementally longer than a maximum time delay generated by any of the base circuit paths.

Long path at-speed testing

A memory system for multiple processors includes a unified memory including a plurality of memory banks, and a memory controller coupled to the unified memory. The memory controller receives requests from the multiple processors, each of the requests including information of a memory address. The memory controller selects one of the memory banks by asserting a request signal only for a memory bank including the requested memory address, and provides the requesting processor with a requested memory operation on the selected memory bank.

Unified memory system for multiple processors and method for controlling the same

An apparatus generally having a register, an adder circuit and a mask circuit is disclosed. The register may be configured to replace a current value with a new value in response to a clock value. The adder circuit may be configured to generate the new value by adding the current value to a delta value. The mask circuit may be configured to mask at least one value among the delta value, the new value and the clock value in response to a mask value having a plurality of bits.

Low power, variable precision DDA for 3D graphics applications

A transmitter circuit improves a noise margin for decoding a common mode signal at a receiver circuit. The transmitter circuit includes a common mode signal transmitter and a noise margin enhancement circuit coupled to a transmission line. The common mode signal transmitter transmits a control message using a common mode signal. The common mode signal has a first voltage level and a second voltage level higher than the first voltage level, and the control message corresponds to a portion of the common mode signal having the first voltage level. The noise margin enhancement circuit raises a voltage level of the common mode signal to a third voltage level higher than the second voltage level for a specific time period from a rising edge of the common mode signal from the first voltage level.

Method and system for improving noise margin in a receiver circuit

A cache controller with an improved cache memory refill operation is presented. After a request from a CPU for a word of information and the word is not found in the cache memory, the cache controller starts a refill operation by which a line of information including the requested word is loaded into the cache memory from a main memory. The cache controller keeps track of the CPU requests. When a requested word appears during the refill operation, the CPU is notified to load the requested word as the word is loaded into the cache memory. Furthermore, the cache controller efficiently takes advantage of free cycles in the refill operation. If the CPU has requested a word in the cache memory, the cache controller reads the word from the cache memory so the CPU can load the word during a free cycle.

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Santa Clara, CA, United States of America

Mark Jon Kwong