Dialog Semiconductor (uk) Limited

Koninklijke Philips Corporation N.v.

Dialog Semiconductor Gmbh

Apple Inc.

Tpo Hong Kong Holding Limited

Dailog Semiconductor (uk) Limited

Mark Johnathan Childs

David Andrew Fish

Jason Roderick Hector

Jens Masuch

Pietro Gallina

Vincenzo Bisogno

Mark Thomas Johnson

Nigel David Young

Paul Collins

Alexandre Tavares

Ian D French

Jindrich Svorc

Michele De Fazio

Carsten Barth

Tiago Patrao

Alan G Knapp

Herbert Lifka

Frank Kronmueller

Roel Van Woudenberg

Nijs Cornelis Van Der Vaart

Hidenori Kobayashi

Kemal Ozanoglu

Iain M Hunter

Martin Faerber

Rupert Howes

Carlos Calisto

Anthony Clowes

Jurgen J L Hoppenbrouwers

Franciscus P M Budzelaar

Andrew Repton

Michele DeFazio

Turan Solmaz

Davud Andrew Fish

Rebecca Tristram

Giulio De Vita

John Mayega

Paul Naish

Ahmed Shaban

Alexandre Taveres

Anthoney Clowes

A solution is provided for adaptive slope compensation in a DC-DC switching converter. Jitter is reduced for on times less than 50% Tpd by using two or more different slopes for the compensation ramp. Additionally, any discontinuities at the 50% duty cycle point are reduced. Details of the compensation ramp are described, where the ramp rate for the first half of the switching period, for on times greater than 50% Tpd, decreases with increasing on time until, at an on time of 100% Tpd, it is approximately zero. In addition, the ramp rate for the second half of the switching period, for on times greater than 50% Tpd, decreases with decreasing on time until, at a duty of 50%, it is equal to the ramp rate used for the first half of the switching period.

Adaptive slope compensation

The clock input of a buck converter is delayed, preventing sub-harmonic oscillation. The function may be achieved by implementing a clock delay generation circuit, configured to delay a next clock pulse by an amount of time directly proportional to the most recent on time of the high-side switch for peak-mode current control, inversely proportional to the most recent on time of the low-side switch for peak-mode current control, inversely proportional to the most recent on time of the high-side switch for valley-mode current control, or inversely proportional to the clock minus the most recent on time of the high-side switch for valley-mode current control.

Preventing sub-harmonic oscillation with clock delay compensation, in a DC-DC switching converter

It is an object of one or more embodiments of the present disclosure to provide a Multiple-Inductor Multiple-Output (MIMO) switching converter to supply several different output voltages. The combination of this MIMO converter with a booster circuit supplies one or more individual cores with current that bypasses the parasitic network. The booster circuit has a wider bandwidth or a faster response when compared to the main MIMO switching converter. The MIMO booster circuit can supply a number of cores with only a single set of shared inductors. The main advantages include a lower component count and a reduced printed circuit board footprint to support multiple cores in a Multiple-Inductor Multiple-Output. The present disclosure makes use of the low duty-cycle of the power peaks and the low statistical likelihood of these peaks occurring for all cores simultaneously.

Power converter supporting multiple high dl/dt loads

A power supply and a method to provide power to a load via a power delivery network are presented. The power delivery network adds a pole and/or zero to a transfer function of the power supply. The power supply has a feedback unit to sense a load voltage at the load and to provide a feedback voltage which is indicative of the load voltage. The power supply has an input amplifier provides an error voltage based on the feedback voltage. The power supply has a power converter to provide power to the power delivery network depending on the error voltage. The power supply has an equalization unit to add a zero and/or a pole to the transfer function of the power supply, such that the pole and/or zero of the power delivery network is partially compensated. The equalization unit is located between an input amplifier and a power converter.

Power supply with power delivery network equalization

A variable efficiency and response buck converter is achieved. The device includes a multi-phase switch, the coupled coils, the filter capacitor, and the load. The multi-phase switch includes the phase control inputs, the circuit common reference, at least two pairs of complementary switches with each switch containing one upper switch and one lower switch, at least two phase control outputs from the complementary switches. The coupled inductive coils are coupled to the phase control outputs to enable weak couplings and strong couplings. Based on the working mode, equivalently the coupled coils can provide strong mutual inductances and weak mutual inductances. The filter capacitors connected to the output of the coupled coils provide high efficiency output to the load.

PWM/PFM drive scheme for mutually coupled inductive coils

The clock input of a buck converter is delayed, and the delay is controlled proportionally to the preceding high-side output switch on time. In the steady state, the high-side switch on time is uniform, and the clock is offset by a fixed amount. When sub-harmonic oscillation begins to occur, the high-side switch on time may increase during a cycle. The longer high-side on time causes the clock to be delayed by an increased amount. This has the effect of increasing the following low-side output switch on time. This further increases the subsequent high-side on time, and counteracts the effects of sub-harmonic oscillation. If the system is properly controlled, loop compensation is implemented correctly and sub-harmonic oscillation is prevented. In addition, the scheme may also be configured for the delay to be controlled proportionally to the preceding low-side output switch on time of the buck converter.

An object of this disclosure is to implement a Buck, Boost, or other switching converter, with a circuit to supply a reference voltage and Adaptive Voltage Positioning (AVP), by means of a servo and programmable load regulation. The reference voltage is modified, achieving a high DC gain, using a servo to remove any DC offset at the output of the switching converter. The correction implemented by the servo is measured, and a programmable fraction of the correction is injected back on either the reference voltage or the output feedback voltage. To accomplish at least one of these objects, a Buck, Boost, or other switching converter is implemented, consisting of an output stage driven by switching logic, with a servo configured between the reference voltage and the control loops of the Buck converter. The AVP function is implemented on either the reference voltage or output feedback voltage.

AVP combined with DAC servo

An asymmetric two-stage DC-DC switching converter, using multi-stage phases, in parallel to single-stage phases, to supply an output voltage, is described. An intermediate voltage supply is used to provide supply to some second-stage phases. Several different silicon dies are used to implement a multi-phase DC-DC switching converter, where different phases are located on different dies, and different silicon processes are used to implement the different dies. The silicon die containing the faster phases, and the fast-response control circuitry, is placed closer to the load, than the silicon die containing the slower phases, and the larger value inductors. A single control signal is used to control all the single-stage and second-stage phases. A way of implementing a control scheme for the second-stage phases that allows them to operate independently from the first-stage phases, but still regulate correctly in the DC-DC switching converter system, is described. Specifically details are provided how offsets between the first-stage and second-stage systems can be reduced or eliminated, with an optional auto-calibration routine.

Asymmetric two-stage DC-DC switching converter

A DC-DC current-control mode switching converter is disclosed, with peak-mode control circuitry, configured to compare a coil current to a variable current limit, to turn off a high side device when the coil current exceeds the variable current limit. The DC-DC switching converter includes a compensation ramp generator, configured to provide a compensation ramp signal, and an offset circuit, configured to provide an offset current. The DC-DC switching converter further includes an amplifier, configured to generate a control current proportional to the difference between an output voltage and a target voltage, and an adder, to combine the control current, the compensation ramp signal, and the offset current. A DC-DC current-control mode switching converter, with valley-mode control circuitry, configured to compare a coil current to a variable current limit, to turn off a low side device when the coil current falls below the variable current limit, is also disclosed.

Compensation ramp offset removal

A servo block in a Buck, Boost, or switching converter allows a positive offset to be applied to the DAC voltage. In a typical switching converter application, the load will have a positive current, sourced from the switching converter to ground through the load. This will cause the output voltage of the switching converter to fall with the output impedance. The servo block corrects the output voltage by adjusting the DAC voltage upwards. In the case where current is forced back into the switching converter, causing the output voltage to rise, the servo block will have affect. The behavior of the servo block is desirable as it reduces the negative affect the servo block may have on load transients occurring when the switching converter is in over voltage. In particular, the idea of shifting the DAC voltage for several different loops with a single servo block is disclosed. This scheme is particularly effective for a switching converter design, allowing the slow loop integrator and fast existing switching converter control loops to be considered almost independently.

DAC servo

An object of this disclosure is to implement a Buck, Boost, or other switching converter, with a circuit to supply a reference voltage and Adaptive Voltage Positioning (AVP), by a servo and programmable load regulation. The reference voltage is modified, achieving a high DC gain, using a servo to remove any DC offset at the output of the switching converter. The correction implemented by the servo is measured, and a programmable fraction of the correction is injected back on either the reference voltage or the output feedback voltage. To accomplish at least one of these objects, a Buck, Boost, or other switching converter is implemented, consisting of an output stage driven by switching logic, with a servo configured between the reference voltage and the control loops of the Buck converter. The AVP function is implemented on either the reference voltage or output feedback voltage.

DC-DC switching converter with adaptive voltage positioning combined with digital-to-analog converter servo

Current in a switching converter is controlled using a current-mode hysteretic controller. The high-side switch (usually a PMOS) is turned off when the current in the coil exceeds a certain peak control current. The low-side switch (usually an NMOS) is turned off when the current in the coil falls below a certain valley control current. A current ramp is added to one of these control currents, either peak or valley. The current ramp is initiated by a reference clock signal, which has the effect of synchronizing the switching converter to the reference clock.

Current mode hysteretic control with clocked ramp

Drive scheme for weakly coupled coils

A DC-DC switching converter is described, with a high magnetic coupling ratio between coils connected directly to a supply and ground, and with pass-device switches connected directly to an output. The pass-device switches are driven in such a way that the coils are magnetized alternately. The DC-DC switching converter may use multiple output switches, to supply multiple outputs. The DC-DC switching converter may use different turns-ratio on the coils, to adjust the duty-cycle of the switching converter operates, for a given supply voltage to output voltage ratio.

Output switched switching converter

The disclosure describes a DC-DC switching converter providing a peak-current servo, employing a pulse-frequency modulation (PFM) control signal and a constant on-time. A Buck, Boost, Buck-Boost, or similar switching converter that supports PFM mode is required, using a fixed on-time scheme for PFM. A final value of the coil current is sampled, and the sampled value of the coil current is compared to a target value for the coil current, to establish whether it is greater or less than the target value. The on-time of the high side device is adjusted to bring the final value of the coil current closer to the target value, using an adaptive coil current measurement.

Pulse-frequency modulation constant on-time with peak-current servo

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Sutton, United Kingdom

Mark Johnathan Childs