International Business Machines Corporation

Mark Jay Charney

Thomas R Puzak

Daniel Arthur Prener

Philip George Emma

Robert K Montoye

Allan Mark Hartstein

Peter Howland Oden

William John Starke

Vijayalakshmi Srinivasan

Arthur R Zingher

Albert Y Chang

Pradeep Kumar Dubey

A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while instructions that are predicted as not useful are discarded. The prediction regarding the usefulness of a prefetching instructions is performed utilizing a branch prediction mask contained in the branch history mechanism. This mask is compared to information contained in the prefetching instruction that records the branch path between the prefetching instruction and actual use of the data. Both instructions and data can be prefetched using this mechanism.

Prefetching using future branch path information derived from branch prediction

A cache memory system for use with an external cache system comprising at least one data array includes one or more cache data arrays and corresponding cache directory arrays. The cache memory system operates in one of at least two modes of operation. In a first mode of operation, the cache data arrays store data relating to directory information stored in the corresponding cache directory arrays. In a second mode of operation, at least a portion of the cache data arrays stores directory information corresponding to the at least one data array of the external cache system.

Cache memory system for selectively storing directory information for a higher level cache in portions of a lower level cache

A mechanism is described that prefetches instructions and data into the cache using a branch instruction as a prefetch trigger. The prefetch is initiated if the predicted execution path after the branch instruction matches the previously seen execution path. This match of the execution paths is determined using a branch history queue that records the branch outcomes (taken/not taken) of the branches in the program. For each branch in this queue, a branch history mask records the outcomes of the next N branches and serves as an encoding of the execution path following the branch instruction. The branch instruction along with the mask is associated with a prefetch address (instruction or data address) and is used for triggering prefetches in the future when the branch is executed again. A mechanism is also described to improve the timeliness of a prefetch by suitably adjusting the value of N after observing the usefulness of the prefetched instructions or data.

Branch history guided instruction/data prefetching

A method and apparatus for storing and utilizing set prediction information regarding which set of a set-associative memory will be accessed for enhancing performance of the set-associative memory and reducing power consumption. The set prediction information is stored in various locations including a branch target buffer, instruction cache and operand history table to decrease latency for accesses to set-associative instruction and data caches.

Method and apparatus for reducing latency in set-associative caches using set prediction

A method for storing information in a computer memory system includes maintaining an M,level storage system including an M,level data store for storing data, an M,level full directory for storing a set of tags corresponding to the data, and an M,level partial directory for storing a subset of the tags. The partial directory is accessible faster than the full directory. Upon an M-1 level miss corresponding to a request for data, a congruence class corresponding to the request is fetched from the partial directory when it is present therein; otherwise, it is fetched from the full directory. The requested data is retrieved from the data store when it is present in the congruence class; otherwise, it is retrieved from a next level of the memory system. The tags in the partial directory may be full tags, partial tags, or a combination thereof.

Methods for caching cache tags

Dynamic migration of a cache prefetch request is performed. A prefetch candidate table maintains at least one prefetch candidate which may be executed as a prefetch request. The prefetch candidate includes one or more trigger addresses which correspond to locations in the instruction stream where the prefetch candidate is to be executed as a prefetch request. A jump history table maintains a record of target addresses of program branches which have been executed. The trigger addresses in the prefetch candidate are defined by the target addresses of recently executed program branches maintained in the jump history table. A pending prefetch table maintains a record of executed prefetch requests. When an operation such as a cache miss, cache hit, touch instruction or program branch is identified, the pending prefetch table is scanned to determine whether a prefetch request has been executed. If a prefetch request has been executed, the prefetch candidate which was used to execute that prefetch request is updated. That is, a new trigger address in the prefetch candidate is selected in order to reduce access latency.

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New York, NY, United States of America

Mark Jay Charney