Nxp B.v.

Cochlear Limited

Mark Janssens

Tom Van Assche

Geert Carron

Steven Mark Thoen

Norbert Philips

Francisco Barat Quesada

A multiprocessor arrangement is disclosed, in which a plurality of processors are able to communicate with each other by means of a plurality of time-sliced memory blocks. At least one, and up to all, of the processors may be able to access more than one time-sliced memories. A mesh arrangement of such processors and memories is disclosed, which may be a partial or complete mesh. The mesh may to two-dimensional, or higher dimensional. A method of communication between processors in a multiprocessor arrangement is also disclosed, in which one or more processors are able to each access a plurality of memories, in each case by time-slicing.

Multiprocessor arrangement having shared memory, and a method of communication between processors in a multiprocessor arrangement

A device including a first integrated circuit (IC), a second IC configured to provide instructions to the first IC based on received data, wherein the first IC is a high-voltage IC and the second IC is a low-voltage IC, and a communication interface between the first and second ICs including a data bus of parallel data lines. The second IC is configured to select, based on the received data, one of a plurality of different communication modes for providing the instructions to the first IC via the communication interface, wherein each mode is defined by a quantity of address data and a quantity of configuration data used to provide the instructions to the first IC.

Inter-chip communications for implantable stimulating devices

A latency control mechanism for a communication system provides a known constant end-to-end delay between an audio source and one or more end node destinations, even in the case where different paths are used to reach the end nodes. A very low jitter time on the end-to-end latency is obtained, and the latency is controllable within a given range in dependence on the constraints imposed by the implementation. A block RX DPLL and latency control unit adjusts the reading moment and position from the RX buffer so that a delay between the time stamp taken at the source side by the transmitter time stamp unit, and the time stamp taken at the receiver side by receiver time stamp unit is constant and equal to a given value.

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Leuven, Belgium

Mark Janssens